Abstract: A first wiring layer overlying a semiconductor substrate has the arrangement of adjacent wirings in the order of first wirings and first shield wirings. A second wiring layer overlying the semiconductor substrate has the arrangement of adjacent wirings in the order of second shield wirings and second wirings to correspond to the respective first wirings and first shield wirings in the first wiring layer. Thus, the capacitance between adjacent wirings is reduced as well as the noise between adjacent wirings. Further, power consumption is reduced without a decrease in the action speed of a signal.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

Abstract: A ferroelectric memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, a plurality of memory cells, a plurality of reference cells, and a control circuit. Each of the bit line pairs is composed of first and second bit lines. Each of the sense amplifiers amplifies a potential difference across the corresponding bit line pair. The memory cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. The reference cells are provided for the respective bit line pairs and each composed of a transistor and a ferroelectric capacitor. In addition, each of the reference cells on each of the bit line pairs retains data different from data of a reference cell on the adjacent bit line pair. The control circuit drives the sense amplifiers, the memory cells, and the reference cells. During the drive of the sense amplifier, the control circuit inactivates a reference word line connected to the reference cell.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: Under application of a voltage V3 to a cell plate line PC, a voltage difference appearing on a bit line BL and an inverted bit line /BL in accordance with a polarized state of a memory cell capacitor and a line capacitance is amplified by a sense amplifier, thereby reading data. A read time for this read operation is tR, which is substantially the same as a write time tWL of L data and a write time tWH of H data. Also, the same voltage is used in a write operation and a read operation. Specifically, the operations are conducted with a write energy larger than a read energy. As a result, a read error can be avoided. Furthermore, since an energy not saturating polarization of a ferroelectric film is used in a write operation, there is no need to provide a voltage increasing circuit, and a high operation can be realized.

Abstract: Object: In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed. Measure to Solve: Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2.

Abstract: The ferroelectric memory device includes a plurality of memory cells arranged in a matrix at crossings of a plurality of word lines and a plurality of bit lines. Each memory cell includes at least one ferroelectric capacitor composed of a ferroelectric film and first and second electrodes sandwiching the ferroelectric film, a memory cell transistor interposed between the bit line and the first electrode of the ferroelectric capacitor, a cell plate line connected to the second electrode of the ferroelectric capacitor, a reset voltage supply line for supplying a voltage of a potential substantially identical to the potential at the cell plate line, a reset transistor interposed between the reset voltage supply line and the first electrode of the ferroelectric capacitor, and a reset control signal line for controlling ON/OFF of the reset transistor.

Abstract: A memory cell transistor using a word line WL as the gate thereof is provided in an active region OD, and a ferroelectric capacitor, including bottom electrode, ferroelectric film and top electrode TE, is formed on a field oxide film. A first interconnection layer is made up of storage lines, each connecting the top electrode TE to one of doped layers of the memory cell transistor, and bit lines, each of which is connected to the other doped layer. In a planar layout, the storage line-intersects only one side of the top electrode TE and the bit line BL does not overlap with the top electrode TE. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. As a result, the reliability of a ferroelectric memory device, including, in a memory cell, a ferroelectric capacitor with a ferroelectric film interposed between the bottom and top electrodes, can be improved.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed. Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2.

Abstract: Under application of a voltage V3 to a cell plate line PC, a voltage difference appearing on a bit line BL and an inverted bit line /BL in accordance with a polarized state of a memory cell capacitor and a line capacitance is amplified by a sense amplifier, thereby reading data. A read time for this read operation is tR, which is substantially the same as a write time tWL of L data and a write time tWH of H data. Also, the same voltage is used in a write operation and a read operation. Specifically, the operations are conducted with a write energy larger than a read energy. As a result, a read error can be avoided. Furthermore, since an energy not saturating polarization of a ferroelectric film is used in a write operation, there is no need to provide a voltage increasing circuit, and a high operation can be realized.

Abstract: A ferroelectric memory device having a memory cell internally provided with first and second ferroelectric capacitors, with first and second memory cell transistors interposed between first and second bit lines (BL, /BL) and the data accumulation nodes (SN, /SN) of the first and second ferroelectric capacitors, respectively, and with a cell plate line (CP) connected to the cell plate of each of the first and second ferroelectric capacitors is controlled by the following procedures. After L data is written in the memory cell capacitor during the period between times t12 and t13, H data is written in the memory cell capacitor by control operation during the period between the time t13 and a time t14. At the time t14, the voltage on a word line (WL) is switched to L to turn OFF the first memory cell transistor, while the writing of H data in the first ferroelectric capacitor is continued by using residual charge.

Abstract: A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.

Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

Abstract: It is an object to present a reading method of a ferroelectric memory device capable of operating at low voltage more securely than in the prior art, and a ferroelectric memory device. To achieve the object, for example, as shown in FIG. 1, after applying a pulse from cell plate signal CP to cell plate electrodes, potentials of bit lines BL0 and /BL0 are respectively set to logic voltage H and L by a sense amplifier. That is, for the cell plate electrode, an electric field is once applied to the ferroelectric capacitor, and the signal application is controlled so as not to apply electric field afterwards, and the potentials of the bit lines are amplified by the sense amplifier.

Abstract: To present a ferroelectric memory device capable of further decreasing fluctuations of reference potential in reference memory cell system. To achieve the object, the ferroelectric memory device comprises, as shown, for example, in FIG. 1, a reference potential generating circuit in a system for generating a reference potential by averaging the potentials being read out from two ferroelectric capacitors for reference memory cells CD00, CD20 storing data of high level, and two ferroelectric capacitors for reference memory cells CD10, CD30 storing data of low level.