Patents by Inventor Hiroyuki Fukuyama

Hiroyuki Fukuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100238694
    Abstract: A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 23, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Fukuyama
  • Publication number: 20100218072
    Abstract: An exemplary memory device has at least one memory chip that stores data and error correcting information. An error detecting circuit in the memory chip performs a calculation on the data and error correcting information to obtain error detection information indicating the locations of bit errors in the data. The uncorrected data and the error detection information are output from the memory chip. The uncorrected data and error detection information may also be output from the memory device, or the memory device may include a memory controller chip with an error correcting circuit that uses the error detection information to correct the bit errors and outputs corrected data from the memory device.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 26, 2010
    Inventors: Hiroyuki Fukuyama, Satoshi Miyazaki
  • Publication number: 20100215987
    Abstract: In a method of manufacturing an aluminum nitride single crystal film on a substrate by heating a sapphire substrate in the presence of carbon, nitrogen and carbon monoxide, an aluminum compound which differs from the raw material sapphire substrate and the formed aluminum nitride single crystal and can control the concentration of aluminum in the heating atmosphere, such as aluminum nitride or alumina, is made existent in a reaction system to promote a reduction nitriding reaction. An aluminum nitride single crystal multi-layer substrate having an aluminum nitride single crystal film on the surface of a sapphire substrate, wherein the aluminum nitride single crystal has improved crystallinity and a low density of defects, is provided.
    Type: Application
    Filed: August 1, 2006
    Publication date: August 26, 2010
    Inventors: Hiroyuki Fukuyama, Kazuya Takada, Akira Hakomori
  • Patent number: 7528462
    Abstract: An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal ?-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a thickness of 10 nm or less in the vicinity of the interface between the both crystals. Threading dislocation is rarely existent in the aluminum nitride single-crystal layer existent on the surface. It is useful as a semiconductor device substrate.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: May 5, 2009
    Assignees: Tokuyama Corporation, Tohoku University, Tokyo Institute of Technology
    Inventors: Hiroyuki Fukuyama, Shinya Kusunoki, Katsuhito Nakamura, Kazuya Takada, Akira Hakomori
  • Patent number: 7437645
    Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 14, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
  • Publication number: 20080226298
    Abstract: The present invention has been achieved to provide a novel optical transmission system realizing high-speed optical transmission over greater distance by suppressing waveform degradation caused by mode dispersion and mode transition in a multimode optical transmission line. The optical transmission system of the present invention includes: an optical transmitter for transmitting incoherent light; an excitation mechanism for exciting a predetermined mode in the incoherent light transmitted from the optical transmitter; a multimode optical transmission line for transmitting the incoherent light transmitted from the excitation mechanism; a transmission mechanism for transmitting a predetermined mode in the incoherent light transmitted from the excitation mechanism; and an optical receiver for receiving the incoherent light transmitted from the transmission mechanism or the incoherent light transmitted from the transmission mechanism.
    Type: Application
    Filed: September 16, 2004
    Publication date: September 18, 2008
    Applicants: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Hiroyuki Fukuyama, Toshihiro Itoh, Satoshi Tunashima, Kimikazu Sano, Koichi Murata, Yohtaro Umeda, Yasuo Tazoh, Hirohiko Sugahara, Hiromu Toba, Masahiro Muraguchi, Senichi Suzuki, Seiji Fukushima, Yoshinori Hibino, Tadashi Sakamoto, Yoshiaki Yamabayashi, Eiji Yoshida, Ryuichi Iwamoto
  • Patent number: 7363558
    Abstract: A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: April 22, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyuki Fukuyama
  • Patent number: 7338555
    Abstract: A highly crystalline aluminum nitride multi-layered substrate comprising a single-crystal ?-alumina substrate, an aluminum oxynitride layer and a highly crystalline aluminum nitride film as the outermost layer which are formed in the mentioned order, wherein the aluminum oxynitride layer has a threading dislocation density of 6.3×107/cm2 or less and a crystal orientation expressed by the half-value width of its rocking curve of 4,320 arcsec or less; and a production process thereof.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: March 4, 2008
    Assignees: Tokuyama Corporation, The Circle for the Promotion of Science and Engineering
    Inventors: Hiroyuki Fukuyama, Wataru Nakao, Shinya Kusunoki, Kazuya Takada, Akira Hakomori
  • Patent number: 7333372
    Abstract: A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: February 19, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hitoshi Tanaka, Hiroyuki Fukuyama, Takeru Yonaga
  • Publication number: 20070208966
    Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.
    Type: Application
    Filed: February 23, 2007
    Publication date: September 6, 2007
    Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
  • Patent number: 7249295
    Abstract: A semiconductor test circuit including an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives serial data including a command code and control data. The controller receives a control signal from the input terminal and outputs an internal control signal. The setting circuit receives serial data from the input terminal and outputs it to the command generator in response to the internal control signal. The command generator then generates an interface signal based on this serial data. The switching circuit receives the signal from one of its ports and outputs the received signal to another port in response to the internal control signal and the command code, and the comparator compares the interface signal received from the command generator with the signal received from the switching circuit.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroyuki Fukuyama, Takeru Yonaga, Hitoshi Tanaka
  • Publication number: 20070161494
    Abstract: A non-oxide ceramics having improved performances and functions by forming a high-quality oxide film on the surface of a non-oxide ceramics such as aluminum nitride. The method for the formation of the non-oxide ceramics comprises the steps of: (1) providing a non-oxide ceramics; (2) introducing the non-oxide ceramics into a furnace and then regulating the atmosphere within the furnace so as to have an oxidizing gas content of not more than 0.5 mmol in terms of total number of moles of the oxidizing gas per m3 of the inside of the furnace; (3) heating the non-oxide ceramics to a temperature at or above a temperature, which is 300° C.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 12, 2007
    Applicants: Tokuyama Corporation, The Circle for the Promotion of Science and Engineering
    Inventors: Hiroyuki Fukuyama, Takehiko Yoneda, Masao Ariyuki, Takeshi Sunaoshi, Hideki Sato
  • Publication number: 20070138710
    Abstract: [PROBLEMS] To provide a metallized non-oxide ceramic shaped article having high adhesive strength between a metal layer and a substrate and the adhesion durability and to provide a process for producing the same. [MEANS FOR SOLVING PROBLEMS] The process for producing a metallized shaped article includes: a heating step of heating a non-oxide ceramic shaped article to a temperature at or above a temperature, which is 300° C.
    Type: Application
    Filed: February 7, 2005
    Publication date: June 21, 2007
    Applicant: The Circle for the Promotion of Science and Engineering
    Inventors: Hiroyuki Fukuyama, Takehiko Yoneda, Shigo Kikutani
  • Patent number: 7220314
    Abstract: A single crystalline aluminum nitride laminated substrate comprising a single crystalline ?-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less. The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide. The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: May 22, 2007
    Assignee: The Circle for the Promotion of Science and Engineering
    Inventors: Hiroyuki Fukuyama, Kazuhiro Nagata, Wataru Nakao
  • Patent number: 7114113
    Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 26, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takeru Yonaga, Hiroyuki Fukuyama, Hitoshi Tanaka
  • Publication number: 20060175619
    Abstract: An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal ?-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a thickness of 10 nm or less in the vicinity of the interface between the both crystals. Threading dislocation is rarely existent in the aluminum nitride single-crystal layer existent on the surface. It is useful as a semiconductor device substrate.
    Type: Application
    Filed: February 6, 2006
    Publication date: August 10, 2006
    Inventors: Hiroyuki Fukuyama, Shinya Kusunoki, Katsuhito Nakamura, Kazuya Takada, Akira Hakomori
  • Patent number: 7054403
    Abstract: A phase lock circuit has a signal path to which a phase comparator, a loop filter and a voltage control oscillator are connected in series, the phase comparator being adapted to compare the phase of an input signal VIN with the phase in the output signal of the voltage control oscillator and to output its result of comparison, the loop filter being adapted to receive the output signal of the phase comparator and to output a DC voltage; the voltage control oscillator being adapted to control the output oscillation frequency depending on the DC output voltage of the loop filter, the phase lock circuit further comprising voltage tracking means for adding, to the voltage of the signal path, a signal causing the average voltage in the output voltage of the phase comparator to coincide with a predetermined reference voltage, whereby the voltage tracking means can enlarge the lock range in the phase lock circuit.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: May 30, 2006
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Hideyuki Nosaka, Hiroyuki Fukuyama, Hideki Kamitsuna
  • Publication number: 20050105348
    Abstract: A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was auto-loaded; and a data comparison circuit which performs a comparison between the data held in the second register and the expected value data stored in the first register, and generates the reset signal based on a result of the comparison.
    Type: Application
    Filed: October 6, 2004
    Publication date: May 19, 2005
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Hitoshi Tanaka, Hiroyuki Fukuyama, Takeru Yonaga
  • Publication number: 20050059257
    Abstract: A highly crystalline aluminum nitride multi-layered substrate comprising a single-crystal ?-alumina substrate, an aluminum oxynitride layer and a highly crystalline aluminum nitride film as the outermost layer which are formed in the mentioned order, wherein the aluminum oxynitride layer has a threading dislocation density of 6.3×107/cm2 or less and a crystal orientation expressed by the half-value width of its rocking curve of 4,320 arcsec or less; and a production process thereof.
    Type: Application
    Filed: September 10, 2004
    Publication date: March 17, 2005
    Inventors: Hiroyuki Fukuyama, Wataru Nakao, Shinya Kusunoki, Kazuya Takada, Akira Hakomori
  • Publication number: 20050034021
    Abstract: A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.
    Type: Application
    Filed: September 10, 2004
    Publication date: February 10, 2005
    Inventor: Hiroyuki Fukuyama