Abstract: A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.

Abstract: A single crystalline aluminum nitride laminated substrate comprising a single crystalline &agr;-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less.

Abstract: A single crystalline aluminum nitride laminated substrate comprising a single crystalline &agr;-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less. The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide. The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.

Abstract: A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

Abstract: A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.

Abstract: A single crystalline aluminum nitride laminated substrate comprising a single crystalline &agr;-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less.

Abstract: For each predetermined operational unit of a semiconductor device for which a logic simulation model is to be generated, several types of operational descriptions (MRS operating sections, bank selecting operating sections, and the like) having different functions are stored in advance as a group of operational description libraries in a hard disk. Then, specifying information which specifies operational descriptions that will be applied to the logic simulation model are inputted. The specified operational descriptions are then read out of the hard disk. Then a model body section which is the core of the logic simulation model is generated based on the read operational description. Thus, a method, an apparatus and a program for generating a logic simulation model, and a recording medium for recording the program, which can greatly reduce the procedures required for generating and maintaining the logic simulation model, are provided.

Abstract: An interface circuit controls access to a dynamic random-access memory having multiple banks, each bank having multiple rows of memory cells, according to received address signals. The address signals are decoded in such a way that when access to a consecutive series of addresses crosses from a first row to a second row, these two rows are always disposed in separate banks. The second row is activated during access to the first row, and the first row is precharged during access to the second row, enabling access to proceed without interruption across the row boundary. In particular, burst access can proceed from row to row continuously.

Abstract: A phase lock circuit has a signal path to which a phase comparator, a loop filter and a voltage control oscillator are connected in series, the phase comparator being adapted to compare the phase of an input signal VIN with the phase in the output signal of the voltage control oscillator and to output its result of comparison, the loop filter being adapted to receive the output signal of the phase comparator and to output a DC voltage; the voltage control oscillator being adapted to control the output oscillation frequency depending on the DC output voltage of the loop filter, the phase lock circuit further comprising voltage tracking means for adding, to the voltage of the signal path, a signal causing the average voltage in the output voltage of the phase comparator to coincide with a predetermined reference voltage, whereby the voltage tracking means can enlarge the lock range in the phase lock circuit.

Abstract: An interface circuit controls access to a dynamic random-access memory having multiple banks, each bank having multiple rows of memory cells, according to received address signals. The address signals are decoded in such a way that when access to a consecutive series of addresses crosses from a first row to a second row, these two rows are always disposed in separate banks. The second row is activated during access to the first row, and the first row is precharged during access to the second row, enabling access to proceed without interruption across the row boundary. In particular, burst access can proceed from row to row continuously.

Abstract: A clock feeding circuit for an integrated circuit includes logic circuit regions, a clock signal source, an input buffer connected to the source, and delay adjusting circuits. Each logic circuit region has a plurality of logic circuits, a buffer circuit for receiving the clock signal and providing it to the logic circuits, and interconnections wiring the logic circuits to the buffer circuit such that clock skew is minimized in the region. The adjusting circuits are disposed between the buffer and the respective logic circuit regions. Each adjusting circuit is composed of a plurality of delay elements, the number of which is pre-selected to determine the delay of the clock signal passing through it.

Abstract: A clock supply circuit having a circuit area includes an input terminal for receiving a clock pulse and a buffer having an input electrically connected to the input terminal and an output. The buffer is disposed in the center of the circuit area. The clock supply circuit also includes a main conductive pattern electrically connected to the output of the buffer. The main conductive pattern is disposed through the center of the circuit area. Each of the branch conductive patterns is electrically connected to the main conductive pattern and extends from the main conductive pattern. Also, each of the branch conductive patterns has a width smaller than the width of the main conductive pattern. Each of the clock receiving circuits is electrically connected to one of the branch conductive patterns and disposed in the circuit area. The number of the clock receiving circuits electrically connected to one branch conductive pattern is same.