Patents by Inventor Hiroyuki Morishita

Hiroyuki Morishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190269494
    Abstract: A gastrointestinal-tract constricting method includes, while observing the gastrointestinal tract by inserting an endoscope into the gastrointestinal tract, forming a spreading block that blocks infiltration of a substance, which damages a mucosa basal layer of the gastrointestinal tract, into the muscular layer underlying the mucosa basal layer, the spreading block being formed along a circumferential direction of the gastrointestinal tract and between the mucosa basal layer and the muscular layer; and supplying the substance along the circumferential direction of the gastrointestinal tract and to a surface of the mucosa that lies within a region that overlaps an inner side of the gastrointestinal tract with respect to the spreading block out of the entire circumference of the gastrointestinal tract in a transverse section of the gastrointestinal tract.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Applicant: OLYMPUS CORPORATION
    Inventors: Takuya OKUMURA, Shunsuke MOTOSUGI, Shinji TAKAHASHI, Takayuki HATANAKA, Hiroyuki MORISHITA
  • Publication number: 20190212644
    Abstract: Provided is a photosensitive composition capable of Ruining a pattern having excellent rectangularity and solvent resistance. Provided are also a cured film, a pattern forming method, a color filter, a solid-state imaging element, and an image display device. This photosensitive composition includes a white or colorless pigment A, an alkali-soluble resin B, a polymerizable compound C having an ethylenically unsaturated double bond, a photopolymerization initiator D1 having a light absorption coefficient of 1.0×103 mL/gcm or more at a wavelength of 365 nm in methanol, and a photopolymerization initiator D2 having a light absorption coefficient of 1.0×102 mL/gcm or less at a wavelength of 365 nm in methanol and a light absorption coefficient of 1.0×103 mL/gcm or more at a wavelength of 254 nm, in which the mass ratio of the photopolymerization initiator D1 to the photopolymerization initiator D2 is photopolymerization initiator D1:photopolymerization initiator D2=90:10 to 40:60.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: FUJIFILM Corporation
    Inventors: Hiroyuki Morishita, Kazuya Oota, Yoshinori Taguchi, Akiko Yoshii
  • Publication number: 20190076283
    Abstract: A gastrointestinal tract constricting method according to the present invention aims to constrict the gastrointestinal tract by contracting a desired region of the gastrointestinal tract by a simple and low-invasive procedure. The method includes forming spreading blocks while observing the gastrointestinal tract with an endoscope inserted into the gastrointestinal tract, the spreading blocks being formed at a position between a mucosa layer and a muscle layer and on both sides of a target region, which is to be damaged by a substance, in a circumferential direction of the gastrointestinal tract so that the spreading blocks block spreading of the substance in the circumferential direction of the gastrointestinal tract to prevent spreading of the substance to an outer side of the target region, and supplying the substance to a mucosal surface of the target region or to the position between the mucosa layer and the muscle layer after formation of the spreading blocks.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Applicant: OLYMPUS CORPORATION
    Inventors: Takuya OKUMURA, Shunsuke MOTOSUGI, Yoshie AIKAWA, Hiroyuki MORISHITA
  • Publication number: 20180371178
    Abstract: A dispersion composition contains a pigment, a dispersant, and a cyclic or chain-like polyester compound. A curable composition contains the above-described dispersion composition. A light-shielding film, a color filter, and a solid-state imaging device contain the curable composition.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 27, 2018
    Applicant: FUJIFILM Corporation
    Inventors: Daisuke HAMADA, Hiroyuki MORISHITA
  • Publication number: 20180317945
    Abstract: An endoscope treatment tool includes: a sheath having a lumen; a basket section protruding from the lumen and having an elastic wire; and an operating wire. The elastic wire has: a maximum section where the outer diameter of the basket section is largest of the elastic wire; a first section that, in a lateral view from a direction orthogonal to a normal from the maximum section to the central axis of the basket section, is largest on the opposite side of the central axis from the maximum section between the maximum section and the proximal end; and a second section that is largest at a position away from the normal between the maximum section and the first section, and in the front view, the first section is located on the opposite side of a straight line orthogonal to the normal at the central axis from the maximum section side.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Applicant: OLYMPUS CORPORATION
    Inventors: Tsutomu OKADA, Hiroyuki MORISHITA
  • Patent number: 10045818
    Abstract: A treatment tool for an endoscope includes a sheath which is extended along a longitudinal axis; a pre-curved portion which is disposed at a distal portion of the sheath; a knife wire lumen which is formed along the longitudinal axis of the sheath; a first communication hole and a second communication hole which are open on an outer circumferential surface to communicate the outer circumferential surface positioned with the knife wire lumen; a wire-shaped cutting portion which is protruded from the first communication hole and the second communication hole, and is extended in a position spaced from the outer circumferential surface and the virtual plane; a fixing portion which is provided to fix an end portion of a wire connected to the cutting portion inside the knife wire lumen, and a bending portion which is provided to bend the wire.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: August 14, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Tsukasa Kobayashi, Yuji Sakamoto, Hiroyuki Morishita, Isamu Nakajima
  • Publication number: 20160338771
    Abstract: A treatment tool for an endoscope includes a sheath which is extended along a longitudinal axis; a pre-curved portion which is disposed at a distal portion of the sheath; a knife wire lumen which is formed along the longitudinal axis of the sheath; a first communication hole and a second communication hole which are open on an outer circumferential surface to communicate the outer circumferential surface positioned with the knife wire lumen; a wire-shaped cutting portion which is protruded from the first communication hole and the second communication hole, and is extended in a position spaced from the outer circumferential surface and the virtual plane; a fixing portion which is provided to fix an end portion of a wire connected to the cutting portion inside the knife wire lumen, and a bending portion which is provided to bend the wire.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Applicant: OLYMPUS CORPORATION
    Inventors: Tsukasa KOBAYASHI, Yuji SAKAMOTO, Hiroyuki MORISHITA, Isamu NAKAJIMA
  • Publication number: 20160331454
    Abstract: A treatment tool for an endoscope, includes a sheath which has a center axis along a longitudinal axis; a pre-curved portion which is disposed at a distal portion of the sheath; a knife wire lumen which has a center axis and is formed along the longitudinal axis; a cutting portion which protrudes from an outer circumference surface positioned at an inward side of the curved shape to outside of the pre-curved portion and extends from a distal end portion toward a proximal end portion of the pre-curved portion; a guide wire accommodation portion which is formed along the longitudinal axis of the sheath; a proximal slit formation portion which is communicated from the guide wire accommodation portion to the outside of the sheath; and a distal slit formation portion which is extended from the proximal end of the pre-curved portion to an intermediate portion of the pre-curved portion.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Applicant: OLYMPUS CORPORATION
    Inventors: Tsukasa KOBAYASHI, Yuji SAKAMOTO, Hiroyuki MORISHITA
  • Patent number: 9317287
    Abstract: To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hiroyuki Morishita
  • Patent number: 9201899
    Abstract: A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 1, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takashi Nishimura, Hiroyuki Morishita
  • Patent number: 8898671
    Abstract: Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Morishita
  • Patent number: 8806466
    Abstract: A program generation apparatus references a source program including a loop for executing a block N times (N?2) and having such dependence that a variable defined in a statement in the block pertaining to ith execution (1?i<N) is referenced by a statement in the block pertaining to jth execution (i<j?N), calculates equivalent representations of variables in the block pertaining to the ith execution and the block pertaining to any other execution than the ith execution, specifies, with respect to each representation of a target variable causing the dependence, a representation of a variable not causing the dependence that is equivalent to the representation of the target variable, and generates a program being for executing the block M times (M?N) and including a statement including the specified representation in place of each representation of the target variable.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: August 12, 2014
    Assignee: Panasonic Corporation
    Inventors: Akira Tanaka, Hiroyuki Morishita, Akihiko Inoue
  • Patent number: 8788793
    Abstract: A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 22, 2014
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Morishita
  • Publication number: 20140136821
    Abstract: To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set.
    Type: Application
    Filed: June 6, 2012
    Publication date: May 15, 2014
    Inventor: Hiroyuki Morishita
  • Publication number: 20140003742
    Abstract: A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 2, 2014
    Inventors: Takashi Nishimura, Hiroyuki Morishita
  • Patent number: 8433884
    Abstract: A multiprocessor executes a plurality of threads without decreasing execution efficiency. The multiprocessor includes a first processor allocating a different register file to each of a predetermined number of threads to be executed from among plural threads, and executing the predetermined number of threads in parallel; and a second processor performing processing according to a processing request made by the first processor. The first processor has areas allocated to the plurality of threads in one-to-one correspondence, makes the processing request to the second processor according to an instruction included in one of the predetermined number of threads, upon receiving a request for writing a value resulting from the processing from the second processor, judges whether the one thread is being executed, and when judging negatively, performs control such that the obtained value is written into one of the areas allocated to the one thread.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: April 30, 2013
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Morishita
  • Publication number: 20120167036
    Abstract: A program generation apparatus references a source program including a loop for executing a block N times (N?2) and having such dependence that a variable defined in a statement in the block pertaining to ith execution (1?i<N) is referenced by a statement in the block pertaining to jth execution (i<j?N), calculates equivalent representations of variables in the block pertaining to the ith execution and the block pertaining to any other execution than the ith execution, specifies, with respect to each representation of a target variable causing the dependence, a representation of a variable not causing the dependence that is equivalent to the representation of the target variable, and generates a program being for executing the block M times (M?N) and including a statement including the specified representation in place of each representation of the target variable.
    Type: Application
    Filed: July 4, 2011
    Publication date: June 28, 2012
    Inventors: Akira Tanaka, Hiroyuki Morishita, Akihiko Inoue
  • Publication number: 20120167114
    Abstract: Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.
    Type: Application
    Filed: July 6, 2011
    Publication date: June 28, 2012
    Applicant: Panasonic Corporation
    Inventor: Hiroyuki Morishita
  • Patent number: 8141088
    Abstract: Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Morishita, Shinji Ozaki, Takao Yamamoto, Masaitsu Nakajima
  • Publication number: 20120060017
    Abstract: A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M instruction streams being input in a state of being distinguished from each other, each of the M instruction streams including Z instructions, M and Z each being an integer of 2 or greater, M×Z being equal to or greater than L; an order information holding unit holding order information that indicates an order of the M×Z instruction storage areas; an extraction unit operable to extract instructions from the M×Z instruction storage areas; and a control unit operable to cause the extraction unit to extract L instructions in executable state from the M×Z instruction storage areas in accordance with the order indicated by the order information, and input the instructions into different ones of the L computing units.
    Type: Application
    Filed: May 18, 2010
    Publication date: March 8, 2012
    Inventor: Hiroyuki Morishita