Patents by Inventor Hiroyuki Nagashima
Hiroyuki Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984167Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: October 17, 2022Date of Patent: May 14, 2024Assignee: Kioxia CorporationInventor: Hiroyuki Nagashima
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Publication number: 20240124047Abstract: A steering control device configured to control a steering device, the steering device including a steering shaft to which a handle is detachably coupled and a motor configured to generate torque that is given to the steering shaft. The steering control device includes a processing circuit configured to execute a process for controlling driving of the motor. The process for controlling the driving of the motor includes a lock process of driving the motor such that a rotation position of the steering shaft is fixed at a specific position, in a state where the handle has been detached from the steering shaft.Type: ApplicationFiled: October 11, 2023Publication date: April 18, 2024Applicants: JTEKT CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Taiki MATSUMOTO, Kenichi ABE, Yuuta KAJISAWA, Yugo NAGASHIMA, Kazuma HASEGAWA, Takashi KOUDAI, Yosuke YAMASHITA, Shintaro TAKAYAMA, Hiroyuki KATAYAMA, Masaharu YAMASHITA
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Publication number: 20230031541Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: October 17, 2022Publication date: February 2, 2023Applicant: Kioxia CorporationInventor: Hiroyuki NAGASHIMA
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Patent number: 11475962Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: December 30, 2020Date of Patent: October 18, 2022Assignee: Kioxia CorporationInventor: Hiroyuki Nagashima
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Publication number: 20210343337Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: July 13, 2021Publication date: November 4, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Patent number: 11100985Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: GrantFiled: February 13, 2019Date of Patent: August 24, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Publication number: 20210118514Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventor: Hiroyuki NAGASHIMA
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Patent number: 10916312Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: July 3, 2019Date of Patent: February 9, 2021Assignee: Toshiba Memory CorporationInventor: Hiroyuki Nagashima
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Publication number: 20190325970Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Applicant: Toshiba Memory CorporationInventor: Hiroyuki NAGASHIMA
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Patent number: 10373692Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: May 17, 2018Date of Patent: August 6, 2019Assignee: Toshiba Memory CorporationInventor: Hiroyuki Nagashima
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Publication number: 20190180816Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: February 13, 2019Publication date: June 13, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Patent number: 10242735Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: GrantFiled: November 3, 2017Date of Patent: March 26, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Publication number: 20180268910Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: May 17, 2018Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventor: Hiroyuki NAGASHIMA
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Patent number: 10020063Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: August 10, 2017Date of Patent: July 10, 2018Assignee: Toshiba Memory CorporationInventor: Hiroyuki Nagashima
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Publication number: 20180053548Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Publication number: 20170365350Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: August 10, 2017Publication date: December 21, 2017Applicant: TOSHIBA MEMORY CORPORATIONInventor: Hiroyuki NAGASHIMA
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Patent number: 9812195Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: GrantFiled: December 23, 2016Date of Patent: November 7, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Patent number: 9767913Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: November 4, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroyuki Nagashima
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Patent number: D888570Type: GrantFiled: January 17, 2019Date of Patent: June 30, 2020Assignee: HISAMITSU PHARMACEUTICAL CO., INC.Inventors: Hiroyuki Nagashima, Hiroyuki Kinoshita, Shigeo Kusumi
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Patent number: D1014284Type: GrantFiled: February 7, 2020Date of Patent: February 13, 2024Assignee: HISAMITSU PHARMACEUTICAL CO., INC.Inventors: Michiaki Tsuji, Hiroyuki Nagashima