Abstract: A process cartridge detachably attached to an image forming apparatus includes a first subunit, a second subunit, a first positioning member, and a second positioning member. The first subunit accommodates a photoconductor therein. The second subunit accommodates a developer applicator therein. The photoconductor and the developer applicator are arranged substantially parallel to each other to define a development gap therebetween. The first positioning member is fastened to both the first and second subunits to position ends of the photoconductor and the developer applicator on a first side of the respective subunits. The second positioning member is fastened to only one of the first and second subunits to position ends of the photoconductor and the developer applicator on a second side of the respective subunits opposite to the first side. An image forming apparatus employing such a process cartridge is also disclosed.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: A lubricant applying unit has a residual-toner collection rate X of 50% when the lubricant applying unit has not been used. The collection rate X is obtained by X=(Ta?Tb)/Ta×100, where Ta is weight per unit area of the residual toner on an area of the image carrier that has not come into contact with the lubricant applying unit, and Tb is weight per unit area of the residual toner on an area of the image carrier that has come into contact with the lubricant applying unit.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes blocks, each of the blocks includes NAND strings that each comprise memory cells serially connected in a first direction, word lines respectively connected to memory cell groups arranged in a second direction in the block, and a controller configured to perform a process (A) of verifying one of states in which all of the memory cells included in the block are turned on (pass) and at least one memory cell is turned off (fail) by use of a first read voltage applied to unselected word lines in a data read time, and to perform a process (B) of reading data from the fail block by use of a second read voltage that is higher than the first read voltage and applied to the unselected word lines.

Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: A nonvolatile semiconductor memory includes: a first semiconductor chip on which a first memory in mounted; a second semiconductor chip on which a second memory is mounted; wherein in the second memory which is a destination for copying, a read enable operation is performed after booting up a command which makes the read enable operation recognize as a write enable operation, and a data of the first memory, which is a source of the copy, is copied to the second memory.

Abstract: A semiconductor memory device comprises a plurality of memory layers arranged in multi layer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: A lubricant applicator includes a solid mold lubricant, a lubricant application roller, and a flicker member. The lubricant application roller scrapes and applies the lubricant to an image bearing member. The flicker member removes a powder substance adhered to the surface of the lubricant application roller and is disposed upstream of the solid mold lubricant in a direction of rotation of the lubricant application roller. The lubricant application roller, the flicker member, and the solid mold lubricant define a sealed space therebetween. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, the flicker member, and an adherence prevention member that prevents the substance removed by the flicker member from adhering again to the lubricant application roller. A lubricant applicator includes the solid mold lubricant, the lubricant application roller, and a lubricant receiver that receives the scraped lubricant from the lubricant application roller.

Abstract: An image forming apparatus includes a photoconductor and a lubricant applicator. The photoconductor carries a toner image formed by developing an electrostatic latent image with a toner. The lubricant applicator applies a solid lubricant to a surface of the photoconductor, and includes a brush roller, a holder, a pressing member, and a protrusion. The holder holds the solid lubricant. The brush roller scrapes off the solid lubricant from the holder and applies the scraped solid lubricant to the surface of the photoconductor. The pressing member has an ellipse shape and presses the solid lubricant toward the brush roller via the holder. The protrusion is disposed on the holder and contacts an inner circumferential surface of the pressing member at two positions provided in both end portions of the pressing member in a direction of a minor axis of the ellipse formed by the pressing member to support the pressing member.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array having a plurality of cell units each including a preset number of memory cells and select gate transistors on drain and source sides. The nonvolatile semiconductor memory device includes a voltage control circuit to prevent occurrence of an erroneous write operation due to excessively high boost voltage of a channel when “1” is written into the memory cell.

Abstract: A lubricant applicator includes: a lubricant application unit that is arranged so as to be in contact with a surface of an image carrier, scrapes a solid lubricant, and applies the solid lubricant onto the surface of the image carrier while moving a surface of the lubricant application unit; a lubricant holding member that holds the solid lubricant; and a lubricant biasing unit that biases the solid lubricant against the lubricant application unit. The lubricant biasing unit is housed in a housing under a state that one end of the lubricant biasing unit is held by the lubricant holding member so that a position of the one end of the lubricant biasing unit is restricted, and another end of the lubricant biasing unit is held by a biasing-unit holding member that is provided to restrict a position of the another end of the lubricant biasing unit.

Abstract: A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.