Patents by Inventor Hiroyuki Nagashima
Hiroyuki Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9767913Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: November 4, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroyuki Nagashima
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Patent number: 9685236Abstract: A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.Type: GrantFiled: January 5, 2017Date of Patent: June 20, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nagashima
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Patent number: 9665426Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.Type: GrantFiled: November 19, 2015Date of Patent: May 30, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jiezhi Chen, Kuniharu Takahashi, Hiroyuki Nagashima, Yuichiro Mitani, Katsuki Matsudera, Kazunori Kanebako
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Publication number: 20170117050Abstract: A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventor: Hiroyuki NAGASHIMA
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Publication number: 20170103807Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: December 23, 2016Publication date: April 13, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Publication number: 20170053704Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: November 4, 2016Publication date: February 23, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Hiroyuki NAGASHIMA
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Patent number: 9543011Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: GrantFiled: March 25, 2016Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Patent number: 9543027Abstract: A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.Type: GrantFiled: March 3, 2014Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Nagashima
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Patent number: 9524786Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: GrantFiled: December 10, 2014Date of Patent: December 20, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Nagashima
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Publication number: 20160217035Abstract: According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.Type: ApplicationFiled: November 19, 2015Publication date: July 28, 2016Inventors: Jiezhi CHEN, Kuniharu Takahashi, Hiroyuki Nagashima, Yuichiro Mitani, Katsuki Matsudera, Kazunori Kanebako
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Publication number: 20160203867Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: March 25, 2016Publication date: July 14, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Patent number: 9324427Abstract: A nonvolatile semiconductor memory device includes: a cell array including MATs (unit cell arrays) arranged in matrix, each of the MATs having memory cells, each of the memory cells having a variable resistive element of which resistance is nonvolatilely stored as data; and write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.Type: GrantFiled: September 8, 2014Date of Patent: April 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Patent number: 9299426Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: GrantFiled: January 5, 2015Date of Patent: March 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Nagashima, Hirofumi Inoue
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Publication number: 20150380094Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.Type: ApplicationFiled: September 10, 2015Publication date: December 31, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki NAGASHIMA
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Patent number: 9165665Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.Type: GrantFiled: May 13, 2014Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nagashima
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Publication number: 20150138888Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.Type: ApplicationFiled: December 10, 2014Publication date: May 21, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Hiroyuki NAGASHIMA
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Publication number: 20150124518Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.Type: ApplicationFiled: January 5, 2015Publication date: May 7, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki NAGASHIMA, Hirofumi INOUE
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Publication number: 20150078094Abstract: A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.Type: ApplicationFiled: March 3, 2014Publication date: March 19, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki NAGASHIMA
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Patent number: RE45480Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.Type: GrantFiled: October 24, 2013Date of Patent: April 21, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Nagashima, Hirofumi Inoue, Hideyuki Tabata, Masanori Komura, Eiji Ito
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Patent number: RE45817Abstract: A nonvolatile semiconductor memory device includes a memory cell array where a plurality of memory cell layers having a plurality of first and second wires which cross each other and a memory cell provided at each intersection of these first and second wires are laminated on top of each other, wherein the memory cells have a variable resistance element and a non-ohmic element laminated in the direction in which the memory cell layers are laminated and tapered in such a manner that the area in a cross section gradually becomes smaller from the bottom memory cell layer towards the top memory cell layer, and the variable resistance element and the non-ohmic element in the memory cells in a certain memory cell layer are laminated in the same order as the variable resistance element and the non-ohmic element of the memory cells in another memory cell layer.Type: GrantFiled: February 7, 2014Date of Patent: December 8, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Nagashima