Abstract: A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.

Abstract: A semiconductor device has a field insulating film formed on a semiconductor substrate, a resistor and a fuse formed on the field insulating film, a first interlayer insulating film formed on the fuse, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film including an SOG layer and formed on the second interlayer insulating film. A passivation oxide film is formed on the third interlayer insulating film. A fuse opening is formed above the fuse and extends from the passivation oxide film to a midpoint in the second interlayer insulating film. A passivation nitride film covers the passivation oxide film and is disposed on a side surface and a bottom surface of the fuse opening. The passivation nitride film disposed on the bottom surface of the fuse opening has an opening exposing the second interlayer insulating film at the midpoint thereof.

Abstract: In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal and a second external connection terminal connected to a VSS, a seal ring wire is connected in parallel, by a connection wire, to a first internal wire extending from the second external connection terminal to the source of the off transistor, and a parasitic resistance of the first internal wire is smaller than a parasitic resistance of a second internal wire connecting the source of the off transistor and a source of the output element to each other.

Abstract: A storage device includes a housing accommodating a storage medium; a printed circuit board having a first side on which electronic components of the storage device are mounted and a second side opposite to the first side, a label overlying the second side of the printed circuit board, the label comprising a base layer and a metal film formed on a surface of the base layer, the metal film being attached to the second side of the printed circuit board, and an insulating layer between the second side of the printed circuit board and a portion of the label.

Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.

Abstract: In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal and a second external connection terminal connected to a VSS, a seal ring wire is connected in parallel, by a connection wire, to a first internal wire extending from the second external connection terminal to the source of the off transistor, and a parasitic resistance of the first internal wire is smaller than a parasitic resistance of a second internal wire connecting the source of the off transistor and a source of the output element to each other.

Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).

Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).

Abstract: A semiconductor device has a field insulating film provided on a semiconductor substrate, and a fuse provided on the field insulating film and having a fuse trimming laser irradiation portion and fuse terminals. The semiconductor device further includes an intermediate insulating film covering the fuse, a first TEOS layer on the intermediate insulating film, an SOG layer for planarizing the first TEOS layer, a second TEOS layer on the SOG layer and on the first TEOS layer, a protective film on the second TEOS layer, and an opening portion above the fuse trimming laser irradiation portion in a region from the protective film to the first TEOS layer. A seal ring is provided on the intermediate insulating film so as to surround the opening portion. The seal ring is disposed over the fuse so as to overlap each of the fuse terminals in plan view.

Abstract: Provided is a semiconductor device which prevents deterioration of the long-term reliability caused by entry of moisture owing to a fuse opening in a multilayer wiring process. In order to prevent entry of moisture through the fuse opening, interlayer insulating films which are oxide films are etched so as to leave a part of a plasma TEOS oxide film layer. After that, a passivation nitride film is deposited and patterned, and then, the passivation nitride film is partly removed, thereby obtaining a structure in which side walls and a side bottom surface of the interlayer insulating films in the fuse opening are covered with the passivation nitride film. This enables inhibition of entry of moisture through an interface among the stacked interlayer insulating films and through an SOG layer, and deterioration of the IC characteristics owing to moisture can be prevented.

Abstract: The presently disclosed subject matter provides DNA molecules designed to down regulate the expression of MMP genes in a cell. Also provided are compositions comprising the DNA molecules. The presently disclosed subject matter further provides methods of using the DNA molecules to inhibit metastasis of a cancer cell. The presently disclosed subject matter also provides methods of using the DNA molecules to modulate tumor growth in a subject.

Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: Provided is a method of manufacturing a semiconductor device capable of preventing, in a SOG etch back planarization process in a multi-layered wiring process, degradation in long-term reliability with respect to the entering of moisture caused by a fuse opening portion. A fuse is shaped so that polycrystalline silicon extends to a lower part of a guard ring provided in a first layer of metal for preventing the entering of moisture from the fuse opening portion. Thus, a metal wiring used for connection to an electrode of the fuse and a metal wiring of the guard ring become equal in height, and hence an SOG layer can be prevented from reaching the inside of an IC.

Abstract: The invention provides a surface-treated calcium carbonate that when incorporated into a paste resin, can impart low viscosity and high thixotropy and offers excellent storage stability, and paste resin compositions containing the same. The surface-treated calcium carbonate is a calcium carbonate surface-treated with a surface treatment agent containing a sodium salt or potassium salt of a fatty acid, wherein the total content of a sodium salt and a potassium salt of lauric acid, a sodium salt and a potassium salt of palmitic acid and a sodium salt and a potassium salt of stearic acid in the surface treatment agent is 80% by weight or more, the content of the sodium salt and potassium salt of lauric acid is within the range of 30% to 60% by weight, the content of a sodium salt and a potassium salt of an unsaturated fatty acid in the surface treatment agent is 5% by weight or less, and the BET specific surface area is 10 m2/g or more.

Abstract: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.

Abstract: A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.

Abstract: The invention provides a surface-treated calcium carbonate that when incorporated into a paste resin, can impart low viscosity and high thixotropy and offers excellent storage stability, and paste resin compositions containing the same. The surface-treated calcium carbonate is a calcium carbonate surface-treated with a surface treatment agent containing a sodium salt or potassium salt of a fatty acid, wherein the total content of a sodium salt and a potassium salt of lauric acid, a sodium salt and a potassium salt of palmitic acid and a sodium salt and a potassium salt of stearic acid in the surface treatment agent is 80% by weight or more, the content of the sodium salt and potassium salt of lauric acid is within the range of 30% to 60% by weight, the content of a sodium salt and a potassium salt of an unsaturated fatty acid in the surface treatment agent is 5% by weight or less, and the BET specific surface area is 10 m2/g or more.

Abstract: A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).

Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).