Abstract: A complementary MOS semiconductor device is provided which is manufactured at low cost and in a short manufacturing period, which enables low voltage operation, and has low power consumption and high driving capability, and which can realizes a power management semiconductor device or an analog semiconductor device at high speed operation. A gate electrode of a CMOS is formed of p-type polycrystalline silicon of a singe polarity or a p-type polycide structure. A PMOS is of surface channel type, and thus, enables a shorter channel and a lower threshold voltage. Also, an NMOS of buried channel type has an extremely shallow buried channel since arsenic having a small diffusion coefficient is used as an impurity for threshold control in the NMOS, and thus, enables a shorter channel and a lower threshold voltage.

Abstract: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of the wells. Therefore, there is the problem that the resistance value is varied by potential variations. Island-like silicon active layer and buried insulation film are formed by etching. Side spacers made of polycrystalline silicon are formed on the sidewalls of step portions of the island-like silicon active layer, buried insulation film, and semiconductor support substrate. The potentials at the side spacers are controlled. Thus, resistance value variations due to variations in the potential difference between the semiconductor support substrate and the resistor can be suppressed. Furthermore, accurate potential division owing to each resistor is facilitated.

Abstract: There is provided a manufacturing method for a structure capable of realizing a power management semiconductor device and an analog semiconductor device in which a cost is low, a work period is short, and low voltage operation is possible, which have low power consumption and high drive capacity, and which is high function and high precision. The manufacturing method is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for respective gate electrodes of an NMOS transistor and a PMOS transistor as divided by a conductivity type thereof in a CMOS transistor. In addition, a resistor used for a voltage dividing circuit and a CR circuit is formed by using a polycrystalline silicon film as a layer different from the gate electrode, so that higher precision resistor can be provided.

Abstract: The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: There is provided a manufacturing method using a structure capable of realizing a power management semiconductor device and an analog semiconductor device, in which low costs, short manufacturing periods, and low voltage operation are possible, which have low consumption power, high drive power, high grade function, and high accuracy. With respect to the power management semiconductor device and the analog semiconductor device which each include a CMOS transistor and a resistor, the manufacturing method is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for respective gate electrodes of an NMOS transistor and a PMOS transistor as divided by a conductivity type thereof in a CMOS transistor.

Abstract: A semiconductor device structure using an SOI substrate is provided along with a method of manufacturing the structure, and the structure makes it possible to reduce parasitic capacitance while preventing the parasitic bipolar effect caused by the floating substrate effect and preventing supporting substrate bias from changing the threshold voltage. The semiconductor device using an SOI substrate is characterized in that a P-well diffusion layer or an N-well diffusion layer is formed only in a body region located below a gate electrode in a semiconductor thin film.

Abstract: The present invention relates to a field effect transistor formed on a semiconductor thin film formed on an insulating substrate, and to an integrated circuit thereof. Provided is a structure such that a maximum allowable voltage in an output voltage is improved and a bipolar transistor is attained. A field effect transistor according to the present invention employs a structure in which a body contact region is interposed between source regions in order to realize a higher maximum allowable voltage with a smaller area. In order to realize the bipolar transistor with an increased channel width without external wirings for fixing a body potential, a structure of a transistor is also formed in which a drain/source region, a first gate electrode, a portion where a body contact region is arranged with a second region having a first conductivity type, a second gate electrode, and a source/drain region are arranged.

Abstract: A complementary MOS semiconductor device is provided which is manufactured at low cost and in a short manufacturing period, which enables low voltage operation, and has low power consumption and high driving capability, and which can realizes a power management semiconductor device or an analog semiconductor device at high speed operation. A gate electrode of a CMOS is formed of p-type polycrystalline silicon of a singe polarity or a p-type polycide structure. A PMOS is of surface channel type, and thus, enables a shorter channel and a lower threshold voltage. Also, an NMOS of buried channel type has an extremely shallow buried channel since arsenic having a small diffusion coefficient is used as an impurity for threshold control in the NMOS, and thus, enables a shorter channel and a lower threshold voltage.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: A ice making machine having a plurality of novel ice making plates or more preferably cylindrical ice making plates, which is formed to be longitudinal cell type wherein said ice making plates proper can be integrally fabricated by extrusion or drawing of heat conductive material, to have a means of fixing cooling tubing thereto by expanding, to be constructed said ice making plates proper and distance pieces made of heat insulating material being piled up alternately upon each other, to be constructed said cooling tubing being fixed thereto by expanding and thus to be assembled ice making plates having a predetermined size and number of ice cube making chambers therein.

Abstract: The invention provides calcium carbonate particles comprising a core and projections formed thereon, and process for preparing same. The calcium carbonates of this invention are useful as fillers and pigments for rubbers, plastics, papers, etc. because of their peculiar configuration and unique properties.

Abstract: The filled paper is filled with at least one of (i) a calcium carbonate in the form of particles comprising a core about 0.5 to about 6.5 .mu.m in average diameter and about 100 to about 4000 projections formed on the surface of the core and having a length (L) of about 0.25 to about 2.00 .mu.m, a diameter (D) of about 0.08 to about 0.20 .mu.m and an aspect ratio (L/D) of about 3 to about 10, the calcium carbonate having a void volume of about 1.0 to about 1.8 ml/g and an oil absorption of about 45 to about 60 ml/100 g, and (ii) a calcium carbonate in the form of particles comprising a core about 0.2 to about 2.0 .mu.m in average diameter and about 100 to about 4000 projections formed on the surface of the core and having a length (L) of about 0.15 to about 4.00 .mu.m, a diameter (D) of about 0.05 to about 0.20 .mu.m and an aspect ratio (L/D) of about 3 to about 20, the calcium carbonate having a void volume of about 1.8 to about 3.3 ml/g and an oil absorption of about 50 to about 100 ml/100 g.

Abstract: Calcium carbonate is dispersed by a dispersant comprising a salt of an acrylic acid/maleic acid copolymer.

Abstract: Surface-treated calcium carbonate powders of this invention are easy to handle and highly dispersible in water, give slurries of high concentration and are useful as pigments and various other applications.

Abstract: Precipitated calcium carbonate of uniform particle size is produced by contacting a suspension of calcium hydroxide with a carbon dioxide-containing gas in three steps. The particle size of precipitated calcium carbonate can be optionally selected by suitably adjusting reaction conditions.

Abstract: Cubic calcium carbonate crystals of uniform size are prepared by contacting with CO.sub.2 a starting aqueous suspension containing Ca(OH).sub.2 and cubic CaCO.sub.3 crystals less than 0.1.mu.m in size, adding Ca(OH).sub.2 to the suspension resulting from the first step and contacting the resultant mixture with CO.sub.2.