Abstract: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O) in spin-coating on the surface of the semiconductor substrate (11) in a centrifugal force acting direction (F) along the surface of the semiconductor substrate (11) and located in a forward side of the centrifugal force acting direction (F), has a curved surface convex to the forward side of the centrifugal force acting direction (F) when the semiconductor substrate (11) is seen in a plan view.

Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type disposed in contact with the semiconductor thin film. A gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.

Abstract: A X-ray inspection device for inspecting a solder connection portion between a circuit device having a solder ball and a printed circuit board having a land includes: X-ray irradiating means for irradiating X-ray to the solder connection portion between the solder ball and the land; X-ray detecting means for detecting the X-ray transmitted through the solder connection portion and for outputting a detection signal; and image forming means for forming and outputting a horizontal tomographic image of the solder connection portion on the basis of the detection signal. The horizontal tomographic image shows existence or nonexistence of a solder bump disposed on a side of the land.

Abstract: An ESD protection circuit with a reduced area is provided whose ESD protection device protects an internal element against ESD while ensuring sufficient. ESD strength in a power management semiconductor device having a fully depleted SOI device structure and in an analog semiconductor device. An NMOS protection transistor formed on an SOI semiconductor thin film layer is used as the ESD protection device at an output terminal of an internal element that is a fully depleted SOI CMOS formed on a semiconductor thin film layer, especially an NMOS output terminal, while an NMOS protection transistor formed on a semiconductor support substrate is used for input protection of the internal element.

Abstract: A semiconductor device has a semiconductor support substrate, a buried insulation film disposed on the semiconductor support substrate, and a single-crystal silicon active layer disposed on the buried insulation film. The buried insulation film has portions which have been removed so that remaining portions of the buried insulating film form buried insulating film island regions. The single-crystal silicon active layer has portions which have been removed so that remaining portions of the single-crystal silicon active layer form single-crystal silicon active layer island regions defining single-crystal silicon resistors of a resistance circuit.

Abstract: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of the wells. Therefore, there is the problem that the resistance value is varied by potential variations. Island-like silicon active layer and buried insulation film are formed by etching. Side spacers made of polycrystalline silicon are formed on the sidewalls of step portions of the island-like silicon active layer, buried insulation film, and semiconductor support substrate. The potentials at the side spacers are controlled. Thus, resistance value variations due to variations in the potential difference between the semiconductor support substrate and the resistor can be suppressed. Furthermore, accurate potential division owing to each resistor is facilitated.

Abstract: Provided is a structure in which a gate electrode of an MMOS transistor of a fully depleted SOT CMOS circuit formed on a semiconductor thin film has an N-type conductivity, while a gate electrode of an protection NMOS transistor as an ESD input/output protection element formed on a semiconductor support substrate has a P-type conductivity, making it possible to protect input/output terminals, especially, an output terminal of a fully depleted SOI CMOS device, which is weak against ESD noise, while ensuring a sufficient ESD breakdown strength.

Abstract: The presently disclosed subject matter provides DNA molecules designed to down regulate the expression of MMP genes in a cell. Also provided are compositions comprising the DNA molecules. The presently disclosed subject matter further provides methods of using the DNA molecules to inhibit metastasis of a cancer cell. The presently disclosed subject matter also provides methods of using the DNA molecules to modulate tumor growth in a subject.

Abstract: An information providing device, which provides information (such as web page) to a client device via a network, includes: a usage history storing unit that stores a usage history of each web page into a usage history database, and calculates a utilization rate of each web page based on the usage history; a display style changing unit that changes a style of displaying a link to the web page or the web page itself based on the utilization rate and display settings; and a display settings changing unit that changes the display settings according to an instruction from a user and stores the display settings in a display settings storage unit.

Abstract: The invention aims to reduce the size of a disk clamp mechanism to be built into a disk player. The clamp mechanism comprises: a disk clamp portion formed integrally with a turntable; a clamper; and a damper holder for holding the damper via a damper mounting shaft adapted to hold the damper in rotatable fashion, wherein a flange portion provided at an end of the damper mounting shaft is placed within a space formed inside the clamper. The damper comprises a peripheral portion and a chamber portion in which the space is formed, and the disk clamp portion has a recessed groove portion engageable with the chamber portion, the structure being such that, when the disk is clamped, the end portion of the chamber portion is accommodated into the disk clamp portion, thus achieving a size reduction by reducing the height in a direction perpendicular to the disk.

Abstract: An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film. The insulated gate transistor is controlled by injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region, and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.

Abstract: Submitted herewith is a check in the amount of $650.00 to cover the additional fee for thirteen (13) claims in excess of twenty total. Should the check prove insufficient for any reason or should an additional fee be due, authorization is hereby given to charge any such deficiency or additional fee to our Deposit Account No. 01-0268.

Abstract: A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures are taken in which a gate is divided into division gates, and electric potentials which are closer to a drain electric potential and which change according to increase or decrease in the drain electric potential are supplied to the division gates nearer a drain, respectively.

Abstract: A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor for a standard power supply voltage of the IC or LSI or by utilizing it's process technique. In order to increase an operating voltage of a field effect transistor, a measure is taken in which a gate is provided with an electric potential distribution varying in accordance with the drain electric potential.

Abstract: There is provided a manufacturing method using a structure capable of realizing a power management semiconductor device and an analog semiconductor device, in which low costs, short manufacturing periods, and low voltage operation are possible, which have low power consumption, high drive power, high grade function, and high accuracy. With respect to the power management semiconductor device and the analog semiconductor device which each include a CMOS transistor and a resistor, the manufacturing method is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for respective gate electrodes of an NMOS transistor and a PMOS transistor as divided by a conductivity type thereof in a CMOS transistor. In addition, a resistor used for a voltage dividing circuit and a CR circuit is formed by using a polycrystalline silicon film as a layer different from the gate electrode.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.