Abstract: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.

Abstract: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.

Abstract: A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

Abstract: Provided is a semiconductor device including an N-channel high-voltage MOS transistor, in which wiring metal connected to a drain region is laid above a boundary portion between an oxide film formed by LOCOS process or the like on a low impurity concentration region and a high impurity concentration region forming the drain region, to thereby alleviate an electric field concentration at the boundary portion which is a contact portion between the low impurity concentration region and the high impurity concentration region by an electric field generated from the wiring metal toward a semiconductor substrate.

Abstract: A semiconductor device manufacturing method includes a field oxide insulation film forming step, an electrode forming step, and a resistor forming step. The field oxide insulation film forming step comprises forming a field oxide insulation film on a surface of the semiconductor substrate so that a portion which corresponds to a side surface portion for each of active regions formed on the surface of the semiconductor substrate, which opposes a rotation center of the surface of the semiconductor substrate in spin-coating of a photoresist in the electrode forming step, and which is located at a front side of a centrifugal force acting direction along the surface of the semiconductor substrate has a curved surface that is convex in a forward direction of the centrifugal force along the surface of the semiconductor substrate as seen in plan view of the semiconductor substrate.

Abstract: Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.

Abstract: A X-ray inspection device for inspecting a solder connection portion between a circuit device having a solder ball and a printed circuit board having a land includes: X-ray irradiating means for irradiating X-ray to the solder connection portion between the solder ball and the land; X-ray detecting means for detecting the X-ray transmitted through the solder connection portion and for outputting a detection signal; and image forming means for forming and outputting a horizontal tomographic image of the solder connection portion on the basis of the detection signal. The horizontal tomographic image shows existence or nonexistence of a solder bump disposed on a side of the land.

Abstract: In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate.

Abstract: The presently disclosed subject matter provides DNA molecules designed to down regulate the expression of MMP genes in a cell. Also provided are compositions comprising the DNA molecules. The presently disclosed subject matter further provides methods of using the DNA molecules to inhibit metastasis of a cancer cell. The presently disclosed subject matter also provides methods of using the DNA molecules to modulate tumor growth in a subject.

Abstract: A semiconductor device is formed on an SOI substrate having a silicon layer formed on an insulating layer. A transistor element is formed in the silicon layer of the SOI substrate. An isolation film for electrically isolating the transistor element is formed in the silicon layer of the SOI substrate by LOCOS so that a parasitic transistor is formed. Impurity diffusion regions are disposed at an end of the isolation film and at a boundary of a source region of the transistor element with a channel forming region. The impurity diffusion regions have a polarity opposite to that of the source region. A current path due to a parasitic channel in the parasitic transistor is suppressed.

Abstract: The invention aims to reduce the size of a disk clamp mechanism to be built into a disk player. The clamp mechanism comprises: a disk clamp portion formed integrally with a turntable; a clamper; and a clamper holder for holding the clamper via a clamper mounting shaft adapted to hold the clamper in rotatable fashion, wherein a flange portion provided at an end of the clamper mounting shaft is placed within a space formed inside the clamper. The clamper comprises a peripheral portion and a chamber portion in which the space is formed, and the disk clamp portion has a recessed groove portion engageable with the chamber portion, the structure being such that, when the disk is clamped, the end portion of the chamber portion is accommodated into the disk clamp portion, thus achieving a size reduction by reducing the height in a direction perpendicular to the disk.

Abstract: To provide an antibody against FGF23 and a pharmaceutical composition such as a preventive or therapeutic agent which can prevent or treat by suppressing an action of FGF23 by using the antibody. An antibody or its functional fragment against human FGF23 produced by hybridoma C10 (Accession No. FERM BP-10772).

Abstract: A high voltage operating field effect transistor has a substrate, a source region and a drain region which are spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region. At least one of a signal electric potential and a signal current is supplied to the source region, and a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential is supplied to the gate region. One end of a rectifying device is connected to the gate region, and a second constant electric potential is supplied to the other end of the rectifying device.

Abstract: In a method of manufacturing a semiconductor device, a polycrystalline silicon film is deposited on a gate insulating film formed over a substrate and is doped with a P-type impurity to form the first polycrystalline silicon film with a P-type conductivity. A high melting point polycide film is deposited on the P-type first polycrystalline silicon film. The P-type first polycrystalline silicon film, high melting point metallic polycide film, and insulating film are etched to form a gate electrode. A second polycrystalline silicon film different from the P-type first polycrystalline silicon film is deposited on the substrate. The second polycrystalline silicon film is etched to form a resistor composed of the second polycrystalline silicon film.

Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

Abstract: A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

Abstract: A high voltage operating field effect transistor has a substrate, a semiconductor channel formation region disposed in a surface of the substrate, a source region and a drain region which are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region, a gate insulating film region disposed on the semiconductor channel formation region, a resistive gate region disposed on the gate insulating film region, a source side electrode disposed on a source region end portion side of the resistive gate region, and a drain side electrode disposed on a drain region end portion side of the resistive gate region. A signal electric potential is supplied to the source side electrode, and a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential is supplied to the drain side electrode.

Abstract: Where the silicon active layer of an SOI substrate is used as a resistor, it is difficult to form small wells densely in a semiconductor support substrate portion under the resistor because of the presence of a buried insulation film. It is also difficult to control the potential division of the wells. Therefore, there is the problem that the resistance value is varied by potential variations. Island-like silicon active layer and buried insulation film are formed by etching. Side spacers made of polycrystalline silicon are formed on the sidewalls of step portions of the island-like silicon active layer, buried insulation film, and semiconductor support substrate. The potentials at the side spacers are controlled. Thus, resistance value variations due to variations in the potential difference between the semiconductor support substrate and the resistor can be suppressed. Furthermore, accurate potential division owing to each resistor is facilitated.

Abstract: A field oxide film for electrically isolating an NMOS and a PMOS is formed by forming a silicon oxide film in an active layer of an SOI substrate by LOCOS. A bird's beak, where the oxide film becomes thin, is formed at an end of the field oxide film, and a parasitic transistor is formed at the bird's beak. A channel cut region for suppressing leak current due to the parasitic transistor is provided. More specifically, P+ diffusion regions are formed in the NMOS at the bird's beak of the field oxide film at two points of a boundary of an N+ diffusion layer (source) with a P well diffusion layer. By providing the channel cut region, a current path (leak current) due to a parasitic channel in the parasitic transistor can be suppressed when the gate is off.