Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Abstract: A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device.

Abstract: Provided is a multi-chip package memory device. The multi-chip package memory device may include a transmission memory chip and a plurality of memory chips that are stacked on the transmission memory chip. The transmission memory chip may include a temporary storage unit, and may transmit a received command or received data to a corresponding memory chip, or to an external element. Each of the memory chips may include a memory core, and may delay the received command according to the properties of the memory chips and then may output delay commands. The transmission memory chip may store the received data in different portions of the temporary storage unit when the delay commands are respectively received.

Abstract: Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.

Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Abstract: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.