Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided.

Abstract: A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to each one of a plurality of client devices connected to a host device by the daisy chain bus structure may be readily determined.

Abstract: The present invention provides a high-speed memory device that can be easily tested using the existing low-speed Automatic Test Equipment (ATE). In an embodiment of the invention, a memory device includes two channels. During normal communications with a host, one channel is used for bidirectional communications with a host. But during a test mode, a first channel is used to communicate with the ATE in one direction, and a second channel is used to communicate with the ATE in the opposite direction. The present invention also provides a memory module and a method for controlling the high-speed memory device.

Abstract: A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract: A communication system communication system includes a transmitter and a receiver. The transmitter inverts multiple bits of first transmission data, serializes the first transmission data to generate second transmission data, and provides the second transmission data to communication channels, in response to an error signal. The receiver inverts multiple bits of first reception data provided from the communication channels, parallelizes the first reception data to generate second reception data, and generates the error signal based on the second reception data, in response to the error signal.

Abstract: Example embodiments relate to a memory system and a method of controlling power thereof. The memory system may include a memory device and a memory controller. The memory device may be configured to be set to a specific power characteristic mode in response to a mode register set command so as to provide a power characteristic information corresponding to the specific power characteristic mode. The memory controller may be configured to provide the mode register set command to the memory device, configured to read the power characteristic information corresponding to the specific power characteristic mode from the memory device, configured to generate a power control information based on the power characteristic information, configured generate a command in response to the power control information, and provide the command to the memory device according to the power control information.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.

Abstract: A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device.

Abstract: Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Abstract: An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current. The calibration circuit may be configured to generate the reference current based on a reference resistor coupled thereto. In particular, the calibration circuit may be configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor to generate the voltage at the replica of the variable impedance circuit.

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract: A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

Abstract: A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

Abstract: A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.

Abstract: A memory system may include a memory device and a memory controller. The memory device may include a first bank and a second bank. The memory controller may include a read request scheduling queue that may store a read request, and may controls the read request scheduling queue so that if first and the second read requests to the first bank and a third read request to the second bank occur successively, data from the memory device may be output seamlessly by applying a first additive latency to first and second read requests to the first bank, and by applying a second additive latency to a third read request to the second bank.

Abstract: For sensing a target temperature, first and second temperature detectors generate first and second delay signals having negative and positive delay changes with temperature. A comparator senses the target temperature from the first and second delay signals such as by activating an output signal when the temperature is at least the target temperature.

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract: An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.