Abstract: Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k?1)th chip of the first through mth chips, where k is a natural number and 2?k?m, configured to output a (k?1)th detection signal corresponding to a phase difference between (k?1)th test data of the (k?1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k?1)th detection signal.

Abstract: A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

Abstract: A termination circuit is connected to an input buffer receiving a data signal, and includes at least one termination resistor connected to the input buffer for impedance matching. At least one switch controls a connection between the input buffer and a corresponding one of the at least one termination resistors. A control signal generator generates a control signal for selectively enabling the termination circuit by controlling each of the at least one switches. The control signal has an input period less than or equal to an input period of a data signal.

Abstract: A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A memory device may include a memory core block, a data patch unit, a Cyclic Redundancy Check (CRC) generating unit, and/or a serializer. The data patch unit may be configured to patch parallel data read from the memory core block in response to a first read pulse. The CRC generating unit may be configured to generate the CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated. The serializer may be configured to convert the parallel data to serial data in response to the first read pulse, and/or arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract: A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.

Abstract: A communication system communication system includes a transmitter and a receiver. The transmitter inverts multiple bits of first transmission data, serializes the first transmission data to generate second transmission data, and provides the second transmission data to communication channels, in response to an error signal. The receiver inverts multiple bits of first reception data provided from the communication channels, parallelizes the first reception data to generate second reception data, and generates the error signal based on the second reception data, in response to the error signal.

Abstract: A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.

Abstract: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.

Abstract: A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

Abstract: The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

Abstract: The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current.