Abstract: A pixel includes first, second, and third sub-pixels each including an emission area and a non-emission area. Each of the first, second, and third sub-includes a pixel circuit layer; a first electrode on the pixel circuit layer; a pixel defining layer on the first electrode and including an opening to expose an area of the first electrode; an emission layer on the pixel defining layer; a second electrode on the emission layer; a thin film encapsulation layer over the second electrode; a color filter on the thin film encapsulation layer; and an overcoat layer over the color filter. The overcoat layer has a refractive index greater than a refractive index of the color filter. A color filter of the second sub-pixel overlaps a color filter of each of the first and third sub-pixels in the non-emission area.

Abstract: A cathode active material for a lithium secondary battery according to an embodiment includes lithium metal oxide particles containing lithium and nickel, and containing a small amount of cobalt or no cobalt. An average particle diameter, a modulus and a hardness of the lithium metal oxide particles are adjusted to satisfy a desired relation. A lithium secondary battery has improved high-temperature storage properties, structural stability and high power properties.

Abstract: An information handling system includes a display panel having an active area that generates visual images and an inactive area disposed outside the active area. The inactive area having an alignment mark that is invisible to a naked eye.

Abstract: A display device includes a display panel having a folding axis extending in a first direction; and a panel supporter disposed on a surface of the display panel. The panel supporter includes a first layer including a first base resin and first fiber yarns extending in the first direction and dispersed in the first base resin, a second layer disposed on the first layer, the second layer including a second base resin and second fiber yarns extending in a second direction intersecting the first direction and dispersed in the second base resin, and a third layer disposed on the second layer, the third layer including a third base resin and third fiber yarns extending in the first direction and dispersed in the third base resin.

Abstract: An integrated circuit structure includes a substrate, a conductive layer, a plurality of memory devices, a bonding pad, and a source line. The conductive layer is over the substrate. The memory devices are stacked in a vertical direction over the conductive layer. The bonding pad is over the conductive layer. The source line extends upwardly from the bonding pad and has a lower portion inlaid in the bonding pad and an upper portion having a sidewall coterminous with a sidewall of the bonding pad. A top end of the source line has a first lateral dimension greater than a second lateral dimension of the bonding pad.

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

Abstract: An electronic device includes a sensor, a memory, and a display, and a processor. The processor is configured to determine bio-information and blood pressure information of a user measured through the sensor, determine reliability of calibration of the blood pressure information, based on at least one of elapsed time of the calibration, the bio-information, and the blood pressure information, determine, based on the reliability of the calibration, whether an event associated with the calibration occurs, and display a user interface (UI) to request another calibration, through the display, when the event is determined to have occurred.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: An electronic device includes a sensor, a memory, and a display, and a processor. The processor is configured to determine bio-information and blood pressure information of a user measured through the sensor, determine reliability of calibration of the blood pressure information, based on at least one of elapsed time of the calibration, the bio-information, and the blood pressure information, determine, based on the reliability of the calibration, whether an event associated with the calibration occurs, and display a user interface (UI) to request another calibration, through the display, when the event is determined to have occurred.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of the conductive pattern is disposed on the substrate. The conductive pattern has a notch on each of two sidewalls of the bottom portion.

Abstract: An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of the conductive pattern is disposed on the substrate. The conductive pattern has a notch on each of two sidewalls of the bottom portion.

Abstract: An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric layer is disposed on the substrate and has an opening. The first conductive pattern is disposed in the opening. The second conductive pattern is disposed on the first conductive pattern and exposes an exposed portion of the first conductive pattern. The exposed portion of the first conductive pattern has a notch.

Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

Abstract: A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer and exposes a portion of the barrier layer. A protection layer is formed on the barrier layer at the bottom of the first opening. The protection layer is thicker at the central portion while thinner at the edge portion thereof. A portion of the exposed barrier layer is removed by using the protection layer as a mask to form a second opening. The second opening has at least one sub-opening disposed in the barrier layer adjacent to the sidewall of the second opening. A semiconductor device formed with the method is also provided.

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric layer is located on the substrate. The dielectric layer has a plurality of openings, and side walls of the openings have concave-and-convex profile.

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract: Provided is a memory device including a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layers are located on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portions of the isolation structures are located in the substrate and arranged alternately with the tunneling dielectric layers along a first direction. The upper portions of the isolation structures are located on the lower portions. The cap layers are located on the upper portions. A top surface of the cap layer is a planar surface.