Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract: Provided is a memory device including a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layers are located on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portions of the isolation structures are located in the substrate and arranged alternately with the tunneling dielectric layers along a first direction. The upper portions of the isolation structures are located on the lower portions. The cap layers are located on the upper portions. A top surface of the cap layer is a planar surface.

Abstract: Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric layer is located on the substrate. The dielectric layer has a plurality of openings, and side walls of the openings have concave-and-convex profile.

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract: A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first dielectric layer, a first conductive layer, and an isolation structure. The substrate has a trench. The first dielectric layer is disposed on the substrate between two neighboring trenches. The first conductive layer is disposed on the first dielectric layer. The isolation structure, including a step zone and a recessed zone, is disposed in the trench, wherein an upper surface of the step zone is higher than an upper surface of the first dielectric layer.

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract: A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A small contact hole having a large aspect ratio is formed by employing a stop layer with a trench formed therein. A relatively large contact hole is formed above the trench, and the small contact hole is formed below the trench, using properties of the trench and the stop layer to limit the size of the small contact hole.

Abstract: A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition.

Abstract: A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.

Abstract: A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.