Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O2 treatment is performed on the multi-layered semiconductor structure. The Ar/O2 treatment includes exposure of the structure to Ar ion bombardment and O2 molecular oxidation. The Ar/O2 treatment can be used to create a bottle-shaped structure.

Abstract: A patterning method is provided. First, a material layer is formed on a substrate. Thereafter, an ashable layer is formed on the material layer. Afterwards, a patterned transfer layer is formed on the ashable layer, wherein the patterned transfer layer has a critical dimension less than the exposure limit dimension. Further, the ashable layer is patterned using the patterned transfer layer or a complementary layer of the patterned transfer layer as a mask, so as to form a patterned ashable layer. The material layer is then patterned using the patterned ashable layer as a mask.

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O2 treatment is performed on the multi-layered semiconductor structure. The Ar/O2 treatment includes exposure of the structure to Ar ion bombardment and O2 molecular oxidation. The Ar/O2 treatment can be used to create a bottle-shaped structure.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines.

Abstract: A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines

Abstract: A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall.

Abstract: A patterning method is provided. First, a material layer is formed on a substrate. Thereafter, an ashable layer is formed on the material layer. Afterwards, a patterned transfer layer is formed on the ashable layer, wherein the patterned transfer layer has a critical dimension less than the exposure limit dimension. Further, the ashable layer is patterned using the patterned transfer layer or a complementary layer of the patterned transfer layer as a mask, so as to form a patterned ashable layer. The material layer is then patterned using the patterned ashable layer as a mask.

Abstract: A method of forming a semiconductor structure is provided. First, a target layer and a mask layer are sequentially formed on a substrate. Thereafter, a first pattern transfer layer having a plurality of openings is formed on the mask layer. Afterwards, a second pattern transfer layer is formed in the openings of the first pattern transfer layer. The mask layer is then patterned, using the first pattern transfer layer and the second pattern transfer layer as a mask, so as to form a patterned mask layer. Further, the target layer is patterned using the patterned mask layer.

Abstract: A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative species is relatively higher at the beginning of plasma spiking and can reach the wafer surface to reduce the accumulated charge.

Abstract: A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall.

Abstract: Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.

Abstract: A method of detecting an end point of a plasma etching process for etching a first layer on a second layer is described, the first layer producing a first etching product and the second layer a second etching product. Time-dependent intensity [Ij=1 to m(t)] of a number “m” (m?1) of spectral line(s) of the first etching product in emission spectrum of the plasma and that [Ii=1 to n(t)] of a number “n” (n?1) of spectral line(s) of the second etching product in the emission spectrum are collected, wherein “m+n?3” is satisfied. One index of Lm ? ( t ) ? [ = ? i = 1 , j = 1 n , m ? ? I i ? ( t ) I j ? ( t ) ] , Ls ? ( t ) ? [ = ? i = 1 , j = 1 n , m ? ? I i ? ( t ) I j ? ( t ) ] , Lm?(t) {=d[Lm(t)]/dt} and Ls?(t) {=d[Ls(t)]/dt} is calculated in real time and plotted with the time. An etching end-point is identified from the plot of the one index with the time.

Abstract: Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching.

Abstract: A method of detecting an end point of a plasma etching process for etching a first layer on a second layer is described, the first layer producing a first etching product and the second layer a second etching product. Time-dependent intensity [Ij=1 to m(t)] of a number “m” (m?1) of spectral line(s) of the first etching product in emission spectrum of the plasma and that [Ii=1 to n(t)] of a number “n” (n?1) of spectral line(s) of the second etching product in the emission spectrum are collected, wherein “m+n?3” is satisfied. One index of Lm ? ( t ) [ = ? i = 1 , j = 1 n , m ? I i ? ( t ) I j ? ( t ) ] , ? Ls ? ( t ) [ = ? i = 1 , j = 1 n , m ? I i ? ( t ) I j ? ( t ) ] , ? Lm ? ? ( t ) ? { = ? [ Lm ? ( t ) ] / ? t } ? ? and ? ? Ls ? ? ( t ) ? { = ? [ Ls ? ( t ) ] / ? t } is calculated in real time and plotted with the time.

Abstract: Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.

Abstract: Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching.

Abstract: A method for multi-step dielectric etching includes discharge steps between each of the etching steps in order to help release accumulated charge on the wafer produced by the previous etching step. The discharge steps stabilize the plasma discharge in each transition between etching steps. Charge elimination occurs because the negative species is relatively higher at the beginning of plasma spiking and can reach the wafer surface to reduce the accumulated charge.