Patents by Inventor Hong Tan

Hong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159782
    Abstract: This invention relates to an apparatus for conducting immunoassay test. The apparatus includes a groove unit having a groove along a vertical direction configured to hold a rod-shaped portion of a probe along the vertical direction, and a push pin configured to move along a horizontal direction, the push pin being capable of residing at a first position and a second position. A tip of the push pin is capable of pressing the rod-shaped portion of the probe against the groove when the push pin resides at the first position. The distance between the tip of the push pin and the groove is larger than a diameter of the rod-shaped portion of the probe when the push pin resides at the second position.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 16, 2024
    Inventors: Hong Tan, Ming Xia, Yushan Tan, Jun Chen, Erhua Cao, Genqian Li, Robert F. Zuk
  • Patent number: 11982706
    Abstract: The present disclosure relates to burn-in apparatus, transfer method, burn-in chamber, and interchangeable frame thereof for semiconductor devices burn-in process. The burn-in apparatus comprises of a burn-in chamber with an incomplete base which is adapted to be completed and thermally insulated in cooperation with a thermal insulation base of at least one interchangeable frame which is adapted to be removably moved into and docked in the burn-in chamber to complete the burn-in apparatus. The burn-in apparatus comprises the burn-in chamber and at least one frame. The apparatus is complete and thermally insulated when the frame is moved into the burn-in chamber and docked therein. The apparatus is incomplete and thermally uninsulated when the frame is moved out of the burn-in chamber and undocked therefrom.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: May 14, 2024
    Assignee: MSV SYSTEMS & SERVICES PTE LTD
    Inventors: Teck Huat Tan, Chun Hong Low
  • Publication number: 20240136217
    Abstract: A manufacturing system includes a substrate disposed on a conveyer system. The conveyer system includes a pair of side supports. The substrate is moved on the conveyer system until the substrate is disposed over a bottom support block. The bottom support block is raised to physically contact the substrate. A transfer arm module is provided. The transfer arm module includes a flat bottom surface and an opening formed in the flat bottom surface. The transfer arm module is disposed with the flat bottom surface physically contacting the substrate opposite the bottom support block. A vacuum is enabled through the opening of the transfer arm module. The substrate is lifted off the bottom support block using the vacuum. The substrate is moved over a printing pallet using the transfer arm module. The vacuum is disabled when the substrate is in a positioning area of the printing pallet.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 25, 2024
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Hua Hong Tan, Chee Kay Chow, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Wing Keung Lam
  • Publication number: 20240122633
    Abstract: A connective tissue repair device (10) includes a central hub member (12) formed with an aperture, and first and second anchoring members (14, 16) that extend from opposing sides of the central hub member (12). The first and second anchoring members (14, 16) each have a depth that extends between edges, one of the edges being sharp for pushing into tissue.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 18, 2024
    Applicant: Tendonplus Medical Pte. Ltd.
    Inventors: Dotan Tromer, Nir Goldenberg, Chung Hui Tan, Zai Hong Kua
  • Publication number: 20240124426
    Abstract: Disclosed herein are compounds of Formula (I), or pharmaceutically acceptable salts thereof, that are inhibitors of Polo Like Kinase 4 (PLK4). Also disclosed herein are pharmaceutical compositions comprising the compounds of Formula (I), or pharmaceutically acceptable salts thereof, and one or more pharmaceutically acceptable excipients. Further disclosed herein are methods of treating cancer in a subject in need thereof, comprising administering to the subject an amount of a compound of Formula (I), or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 18, 2023
    Publication date: April 18, 2024
    Inventors: Chudi NDUBAKU, Jared Thomas MOORE, Paul Anthony GIBBONS, Jae Hyuk CHANG, F. Anthony ROMERO, Xiaohui DU, Hiroyuki KAWAI, Stephane CIBLAT, Hong WANG, Vincent ALBERT, Lea CONSTANTINEAU-FORGET, Hugo de Almeida SILVA, Dilan Emine POLAT, Amit NAYYAR, Daniel Gordon Michael SHORE, Kejia WU, Joanne TAN
  • Publication number: 20240128163
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 11945004
    Abstract: A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: April 2, 2024
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Hua Hong Tan, Wing Keung Lam, Zong Xiang Cai, Wei Ming Xian, Yao Hong Wu, Tao Hu
  • Publication number: 20240100683
    Abstract: A tool box includes a base element and a cover. The base element and the cover form a box interior for receiving at least one hand-held power tool. The tool box further includes a locking tab for locking the cover to the base element. The locking tab includes an insertion tool holding device for holding at least one insertion tool.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 28, 2024
    Inventors: Zheyan Hong, Chia Chun Kang, Yen Tiong Tan
  • Patent number: 11942460
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Publication number: 20240082836
    Abstract: Introduced here are rotors that can be placed inside of microplate wells that include liquid samples. Each rotor can be comprised of a ferromagnetic material. Accordingly, when a rotor is subjected to an external rotational magnetic field, the rotor spins and agitates the liquid sample inside the corresponding well. The spin speed may be adjusted by changing the rotation speed, direction, and/or orientation of the external rotational magnetic field. The rotor typically includes a central cavity within which a probe can be suspended during the biochemical test.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Hong Tan, Haode Chen, Genqian Li
  • Patent number: 11929351
    Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Publication number: 20240079306
    Abstract: A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Kelvin Tan Aik Boo, Wen Wei Lum, Hong Wan Ng
  • Publication number: 20240079440
    Abstract: A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Oray O. Cellek, Fei Tan, Gershon Rosenblum, Hong Wei Lee, Cheng-Ying Tsai, Jae Y. Park, Christophe Verove, John L Orlowski, Siddharth Joshi, Xiangli Li, David Coulon, Xiaofeng Fan, Keith Lyon, Nicolas Hotellier, Arnaud Laflaquière
  • Publication number: 20240072022
    Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20240071869
    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Publication number: 20240072411
    Abstract: An electronic device includes a metal back cover, a metal frame, a first antenna module and a second antenna module. The metal frame includes a first and a second disconnection portion, a first and a second connection portion. The first and the second connection portion are connected to the metal back cover. The first disconnection portion is separated from the first connection portion, the metal back cover and the second disconnection portion to form a first slot. The second disconnection portion is connected to the second connection portion and is separated from the metal back cover to form a second slot. The first antenna module is connected to the first disconnection portion, and forms a first antenna path. The second antenna module is connected to the second disconnection portion, and forms a second and a third antenna path with the second disconnection portion and the metal back cover.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicant: Pegatron Corporation
    Inventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Chih-Wei Liao, Chia-Hung Chen, Chen-Kuang Wang, Wen-Hgin Chuang, Chia-Hong Chen, Hsi Yung Chen
  • Publication number: 20240071880
    Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Patent number: D1018975
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: Dyson Technology Limited
    Inventors: Emily Mary Menzies, James Robert Alexander Fisher, Wee Guan Tan, Nicklaus Yu, David Oliver Williams, Phey Hong Soh, Stephen Benjamin Courtney
  • Patent number: D1021641
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: April 9, 2024
    Assignee: IPS GROUP INC
    Inventors: David William King, Choor-Hong Tan, Derek Wu, David Andrew Jones
  • Patent number: D1021642
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: April 9, 2024
    Assignee: IPS GROUP INC.
    Inventors: David William King, Choor-Hong Tan, Derek Wu, David Andrew Jones