Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. The 3D memory device can include a structure of a plurality of gate electrodes insulated by a sealing structure over a substrate. The sealing structure can include an airgap between adjacent gate electrodes along a direction perpendicular to a top surface of the substrate. The 3D memory device can also include a semiconductor channel extending from a top surface of the structure to the substrate. The semiconductor channel can include a memory layer that has two portions extending along different directions. The 3D memory device can further include a source structure extending from the top surface of the structure to the substrate and between adjacent gate electrodes along a direction parallel to the top surface the substrate.

Abstract: Methods and systems for managing security in a cloud computing environment are provided. Exemplary methods include: receiving a target, the target specifying workloads of a plurality of workloads to be included in the security policy, the plurality of workloads being associated with the cloud computing environment; identifying nodes and edges in the graph database using the target, the graph database representing the plurality of workloads as nodes and relationships between the plurality of workloads as edges; getting a security intent, the security intent including a high-level security objective in a natural language; obtaining a security template associated with the security intent; and applying the security template to the identified nodes and edges to produce security rules for the security policy, the security rules at least one of allowing and denying communications between the target and other workloads of the plurality of workloads.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method of forming a structure of 3D NAND memory device, including steps of forming a first stack layer on a substrate, forming a first channel hole extending through the first stack layer, forming a block layer on a surface of the first stack layer and the first channel hole, forming a sacrificial layer in the first channel hole, forming a second stack layer on the first stack layer and the sacrificial layer, performing a first etch process to form a second channel hole extending through the second stack layer and at least partially overlapping the first channel hole and to remove the sacrificial layer in the first channel hole, removing the block layer exposed from the second channel hole, and forming a function layer on a surface of the first channel hole and the second channel hole.

Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole.

Abstract: Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device is disclosed. An alternating conductor/dielectric stack is formed at a first side of a chip substrate. A memory string extending vertically through the alternating conductor/dielectric stack is formed. A chip contact is formed at a second side opposite to the first side of the chip substrate and is electrically connected to the memory string. A first interposer contact is formed at a first side of an interposer substrate. A second interposer contact is formed at a second side opposite to the first side of the interposer substrate and is electrically connected to the first interposer contact through the interposer substrate. The first interposer contact is attached to the chip contact.

Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.

Abstract: Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

Abstract: A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.

Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.

Abstract: Embodiments of 3D memory devices are disclosed. A disclosed 3D memory device can comprises an array interconnect layer disposed over an alternating conductor/dielectric stack and including a first array interconnect structure. Tbe 3D memory device can further comprises a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure. A pad can be embedded in the peripheral interconnect layer and electrically connected with the first peripheral device through the first peripheral interconnect structure. The array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure.

Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.

Abstract: Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.