Patents by Inventor Hua Chen

Hua Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985399
    Abstract: A photographing apparatus and an inspection device are provided. The photographing apparatus comprises a camera, a light supplementing structure, and a closed housing; the camera is provided with a lens, and positioned in and connected to the housing; the housing is provided with at least one photographing portion configured to be attached to an object to be photographed, and a space is formed between the lens and the photographing portion; the light supplementing structure is positioned in and connected to the housing, the light supplementing structure is configured to emit light to said object through the space and the photographing portion, and the lens is configured to capture an image of said object via the photographing portion. The inspection device comprises a rack and the photographing apparatus, and the housing is connected to the rack.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: May 14, 2024
    Assignee: SICHUAN ENERGY INTERNET RESEARCH INSTITUTE, TSINGHUA UNIVERSITY
    Inventors: Yongcan Chen, Hua Zhang, Haoran Wang, Yonglong Li, Jialong Li, Zhaowei Liu, Shuang Wang
  • Patent number: 11980694
    Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Hung Chen, Chih-Wen Chiang, Yun-Tung Pai, Yen-Hua Hsiao, Yao-Kuang Su, Yi-Hsuan Lin, Han-Sheng Siao
  • Patent number: 11983680
    Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.
    Type: Grant
    Filed: June 12, 2021
    Date of Patent: May 14, 2024
    Assignee: CHASE SUSTAINABILITY TECHNOLOGY CO., LTD.
    Inventors: Yung-Fa Yang, Tsung-Tien Chen, Shao-Hsin Hsu, Bo-Wei Chen, Chia-Ching Chen, Ming-Hua Tang
  • Patent number: 11984797
    Abstract: The present disclosure provides an adapter circuit including a bus capacitor, a PMOS power transistor, and a sampling control module; a positive terminal of the bus capacitor is connected to a DC bus voltage, and a negative terminal of the bus capacitor is connected to a drain of the PMOS power transistor; a gate of the PMOS power transistor is connected to a drive signal, and a source of the PMOS power transistor is grounded; the sampling control module is used to obtain the drive signal by detecting an AC mains input voltage and a power-down voltage when the bus discharges, so as to turn off the PMOS power transistor after the AC mains input voltage reaches a peak value, and turn on the PMOS power transistor after the power-down voltage reaches a set voltage; the drive signal includes a PMOS Turn-on signal and a PMOS Turn-off signal.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: May 14, 2024
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Faxin Yu, Yihe Wang, Xiaofeng Lv, Hua Chen, Jiongjiong Mo, Zhiyu Wang
  • Patent number: 11984510
    Abstract: The present application discloses a composite metal oxide semiconductor which is a metal oxide semiconductor doped with a rare earth oxide. Even doping the praseodymium oxide or ytterbium oxide at a small doping amount, oxygen vacancies could be suppressed as well as the mobility be maintained; critically, the thin-films made thereof can avoid the influence of light on I-V characteristics and stability, which results in great improvement of the stability under illumination of metal oxide semiconductor devices. The present application also disclose the thin-film transistors made thereof the composite metal oxide semiconductor and its application.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 14, 2024
    Assignee: South China University of Technology
    Inventors: Miao Xu, Hua Xu, Weijing Wu, Weifeng Chen, Lei Wang, Junbiao Peng
  • Patent number: 11980864
    Abstract: A method of operating an integrated circuit includes using a first switching device to couple a bio-sensing device to a first signal path, generating, using the bio-sensing device, a bio-sensing signal on the first signal path in response to an electrical characteristic of a sensing film, using a second switching device to couple a temperature-sensing device to a second signal path, and generating, using the temperature-sensing device, a temperature-sensing signal on the second signal path in response to a temperature of the sensing film. The first and second switching devices, the bio-sensing device, the temperature-sensing device, and the sensing film are components of a sensing pixel of a plurality of sensing pixels of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Patent number: 11981726
    Abstract: The present invention relates to monoclonal antibodies which have high anti-RSV neutralizing titers. The invention further provides for isolated nucleic acids encoding the antibodies of the invention and host cells transformed therewith. The invention yet further provides for diagnostic, prophylactic and therapeutic methods employing the antibodies and nucleic acids of the invention, particularly as a passive immunotherapy agent in infants and the elderly.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: May 14, 2024
    Assignee: Merck Sharp & Dohme LLC
    Inventors: Kalpit A. Vora, Kara S. Cox, Aimin Tang, Zhifeng Chen, Daniel DiStefano, Lan Zhang, Hua-Poo Su
  • Patent number: 11984477
    Abstract: A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Ta Wu, Chui Hua Chen
  • Publication number: 20240153840
    Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Publication number: 20240152880
    Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.
    Type: Application
    Filed: February 13, 2023
    Publication date: May 9, 2024
    Applicant: OBOOK INC.
    Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
  • Publication number: 20240149740
    Abstract: A public transport vehicle charging system is applied to multiple charging stations and an electric vehicle. The public transport vehicle charging system includes a server communicatively connected to the charging stations and the electric vehicle. The server is configured to establish a charging decision model according to multiple historical conditions and a transport schedule. The server is configured to calculate multiple ideal decisions according to the historical conditions and the transport schedule, so as to adjust multiple parameters in the charging decision model. When the electric vehicle drives toward a first charging station according to the transport schedule, the server is configured to input a current condition into the charging decision model, so as to selectively charge the electric vehicle by the first charging station. The current condition includes a current remaining power and a current position of the electric vehicle.
    Type: Application
    Filed: November 21, 2022
    Publication date: May 9, 2024
    Inventors: Yweting TSAI, Shih-I CHEN, Kuo-Hua WU, Yu-Jin LIN, Hong-Tzer YANG
  • Publication number: 20240153842
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20240152386
    Abstract: An artificial intelligence accelerator includes an external command dispatcher, a first data access unit, a second data access unit, a global buffer, an internal command dispatcher, and a data/command switch. The external command dispatcher receives an address and access information. The external command dispatcher sends the access information to one of the first data access unit and the second data access unit, the first data access unit receives first data from a storage device according to the access information, and sends the first data to the global buffer. The second data access unit receives second data from the storage device according to the access information, and sends the second data. The data/command switch receives the address and the second data from the second data access unit, and sends the second data to one of the global buffer and the internal command dispatcher.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 9, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yao-Hua CHEN, Juin-Ming LU
  • Publication number: 20240152731
    Abstract: A hardware-aware zero-cost neural network architecture search system is configured to perform the following. A neural network search space is divided into multiple search blocks. Each of the search blocks includes multiple candidate blocks. The candidate blocks are guided and scored through a latent pattern generator. The candidate blocks in each of the search blocks are scored through a zero-cost accuracy proxy. One of the candidate blocks included in each of the search blocks is sequentially selected as selected candidate blocks, the selected candidate blocks are combined into multiple neural networks to be evaluated, and network potential of the neural networks to be evaluated is calculated according to scores of the selected candidate blocks. One neural network to be evaluated with the highest network potential is selected to determine the corresponding selected candidate blocks.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yao-Hua Chen, Jiun-Kai Yang, Chih-Tsun Huang
  • Patent number: 11976513
    Abstract: An example security gate can include: an outer frame; an outer gate disposed within the outer frame, the outer gate defining a plane and having a plurality of outer gate vertical members, and the outer gate defining an inner gate opening; an inner gate disposed within the outer gate, the inner gate defining a plurality of inner gate vertical members, wherein the inner gate is configured to move vertically within the plane to control access through the inner gate opening, and wherein the plurality of inner gate vertical members are sized to telescope within the plurality of outer gate vertical members as the inner gate is moved; and a locking mechanism to lock the inner gate at a vertical position relative to the outer gate to define an accessible size of the inner gate opening.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 7, 2024
    Assignee: NORTH STATES INDUSTRIES, INC.
    Inventor: Hua Chen
  • Patent number: 11975468
    Abstract: In various examples, a printbar is formed from multiple modular fluid ejection subassemblies joined together through a molding process that provides for a continuous planar substrate surface. A mold may secure the modular fluid ejection subassemblies during a molding process in which a runner conveys a molding material to seams between the joined modular fluid ejection subassemblies.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 7, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Si-lam J. Choy, Michael W. Cumbie
  • Patent number: 11980032
    Abstract: The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 7, 2024
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Xiaoliang Tang, Naoki Tsuji, Haoyu Chen, Hua Shao
  • Patent number: 11977322
    Abstract: A wavelength conversion device includes a substrate, a reflection layer, a wavelength conversion layer, and a first optical layer. The wavelength conversion device has a central axis. The reflection layer is disposed on an upper surface of the substrate. The central axis is perpendicular to the upper surface. The wavelength conversion layer is disposed on the reflection layer and around the central axis, has a complete or partial annular shape, and includes a first region and two second regions. The first region is located between the second regions. The first optical layer is disposed on a surface of the wavelength conversion layer and corresponds to the first region. In an axial direction, an orthographic projection of the first optical layer on the upper surface is not overlapped with an orthographic projection of the second regions on the upper surface. The first optical layer includes first diffusing particles.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: May 7, 2024
    Assignee: Coretronic Corporation
    Inventor: I-Hua Chen
  • Publication number: 20240141537
    Abstract: The present disclosure provides a superhydrophobic and self-cleaning anticoagulant composite coating material and a preparation method and use thereof, and relates to the technical field of biomedical materials. In the coating material provided by the present disclosure, a titanium dioxide nanotube-based structure increases microscopic roughness of a surface of a titanium-based metal substrate, and a hydrophobic modification layer reduces surface energy of the material. The rough structure and the hydrophobic modification layer have a synergistic effect to construct a superhydrophobic surface, making the surface of the material have self-cleaning characteristics and low adhesion. Air can be retained on the surface of the material to form an air layer, thereby reducing the contact area between the material and bacteria and platelets in the blood, and inhibiting adhesion of the bacteria, platelets, and plasma proteins to the material.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 2, 2024
    Applicant: Anhui Medical University
    Inventors: Shunli ZHENG, Qin RAO, Ling WENG, Jinshuang ZHANG, Donghao LIU, Quanli LI, Ying CAO, Jialong CHEN, Xiangyang LI, Hua QIU, Shengzhuo ZHANG, Daojun SHEN
  • Publication number: 20240146501
    Abstract: A method of monitoring a clock signal of a server is provided. The server includes a phase-locked loop (PLL), a baseboard management controller (BMC), and a light emitting unit. The method includes steps of: A) the server executing a time synchronization service to obtain a synchronization mode that the PLL is operating in, where the synchronization mode is one of a free-run mode, a locked mode, and a holdover mode; B) the server updating the synchronization mode to the BMC when executing the time synchronization service; and C) the BMC storing the synchronization mode and controlling the light emitting unit to display in one of a plurality of displaying manners that corresponds to the synchronization mode.
    Type: Application
    Filed: July 10, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Yuan Chen, Po-Wei Chang, Chi-Hua Li