Abstract: A detection circuit is provided herein, which includes a first transistor, a second transistor, a third transistor, a light sensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to the control terminal and the second terminal. The light sensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: An isolated and purified lactic acid bacteria is provided, which is Lactobacillus paracasei PS23 (PS23) and its applications in delaying aging process, improving immunomodulatory activity, reducing, preventing or treating allergic and inflammation, preventing or treating a chronic disorder and/or (vi) preventing and/or treating a mood disorder or a neurological condition.

Abstract: A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.

Abstract: Disclosed embodiments may include a power converter system with fault handling. Embodiments may include first and second power converters each including an output terminal and a control terminal, the first and second power converters to regulate voltage or current at their respective output terminals based on a voltage at their respective control terminals, the output terminals coupled to each other, and the control terminals coupled to each other; wherein the first power converter comprises: a circuit to detect a fault condition associated with the first power converter and to generate a first fault signal at the control terminal of the first power converter after the detecting the fault condition associated with the first power converter; wherein the second power converter comprises: a circuit to change an operating mode of the second power converter after generating the first fault signal at the control terminal of the first power converter.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under- ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A joystick includes a stick head, an actuating component, a substrate, a bearing base, a resilient recovering component and a constraining component. The actuating component has a first end and a second end opposite to each other. The first end is connected to the stick head, and an identification feature is disposed on the second end. The substrate has a detection module used to detect the identification feature and determine motion of the stick head. The bearing base is disposed on the substrate. An opening portion of the bearing base aligns with the detection module and the actuating component. The resilient recovering component is disposed between the substrate and the bearing base. The constraining component is disposed on the resilient recovering component and movably disposed inside the opening portion, and used to abut against the actuating component in a detachable manner.

Abstract: A method of making an integrated circuit includes steps of selecting a first cell and a second cell for an integrated circuit layout from a cell library in an electronic design automation (EDA) system, the first and second cells each having a cell active area, a cell gate electrode, at least one fin of a first set of fins, and a cell border region, each cell also having the active area at an exposed side, and placing the first exposed side against the second exposed side at a cell border. The method also includes operations of aligning at least one fin of the first set of fins with at least one fin of the second set of fins across a cell border.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: A method includes creating a layout design of the integrated circuit after determining a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. Creating the layout design includes forming first-type active zone patterns, forming second-type active zone patterns, generating a gate-strip pattern, and positioning the gate-strip pattern over the first-type active zone patterns and the second-type active zone patterns. Creating the layout design also includes determining whether to generate one or more poly cut patterns that intersect the gate-strip, based on the difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: Provided are use of a rare earth amino acid complex, a polylactic acid composition and a preparation method thereof. The rare earth amino acid complex is formed by complexing a rare earth metal ion with an amino acid; a rare earth element corresponding to the rare earth metal ion is one or more selected from the group consisting of lanthanum, cerium and samarium; and the amino acid is at least one selected from the group consisting of proline, L-phenylalanine, tyrosine and tryptophan.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Abstract: A method that includes: transmitting, by an electronic device, a first detecting signal when the electronic device is in a reverse wireless charging mode; receiving, by the electronic device at a gap moment between at least two adjacent moments at which the first detecting signal is transmitted, a second detecting signal transmitted by a wireless charging device; and if the second detecting signal received by the electronic device meets a preset condition, automatically switching, by the electronic device, from the reverse wireless charging mode to a forward wireless charging mode.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

Abstract: Provided herein are methods for making gamma lactones comprising reacting a carboxylic acid substrate with a heterologous cytochrome P450 (CYP450) protein with carboxylic acid 4-hydroxylase activity.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.