Abstract: This disclosure relates to the fields of applied meteorology, in particular to a visualization analysis method of the tropical cyclone forecast verification index data, which comprises the following steps: acquiring tropical cyclone data; obtaining a track forecast verification index and an intensity forecast verification index of the tropical cyclone with the tropical cyclone data; obtaining a visible view of the tropical cyclone track forecast error and a visible view of the tropical cyclone intensity forecast error according to the track forecast verification index and the intensity forecast verification index, and in combination with the geographic information of the tropical cyclone; obtaining a first error and a second error according to the track forecast verification index, and obtaining a joint distribution map of the first error and the second error by using the first error and the second error; obtaining a composite box-shaped histogram through the intensity forecast verification index.

Abstract: A method for constructing a design concept generation network (DCGN) and a method for automatically generating a conceptual scheme are provided. A DCGN includes a Transformer encoder, a Transformer decoder, an importance constraint matrix generation module, an importance constraint embedding layer, a cross-attention (CA) layer, and an optimization module. A word importance constraint is ingeniously introduced based on an attention mechanism of a Transformer to record input word constraint information contained in a generated text sequence. This can effectively ensure the reliability and effectiveness of a generated conceptual scheme and is conducive to capturing potential semantic importance information and implementing semantic knowledge reasoning.

Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Abstract: Circuits and methods for adding a Current Mode signal into a Voltage Mode controller for fixed-frequency DC-to-DC power converters. A current-controlled voltage source (CCVS) generates a voltage proportional to the power converter output current, which voltage is combined with a comparison signal generated by comparing a target output voltage to the actual output voltage. The modified comparison signal generates a pulse-width modulation control signal that regulates the power converter output as a function of output voltage and some portion of output current. With the addition of an inductor current signal into the controller Voltage Mode feedback loop, the double pole predominant in constant conduction mode (CCM) mode can be smoothed over to improve stability, while discontinuous conduction mode (DCM) loop response is largely unchanged with or without the added Current Mode signal. Embodiments enable simplified compensation while covering a wider operating range.

Abstract: A programmable two-dimensional simultaneous multi-beam optically operated phased array receiver chip is manufactured based on silicon-on-insulator (SOI) and indium phosphide (InP) semiconductor manufacturing processes, including the SiN process. The InP-based semiconductor is used for preparing a laser array chip and a semiconductor optical amplifier array chip, the SiN is used for preparing an optical power divider, and the SOI semiconductor is used for preparing a silicon optical modulator, a germanium-silicon detector, an optical wavelength multiplexer, a true delay line, and other passive optical devices. The whole integration of the receiver chip is realized through heterogeneous integration of the InP-based chip and the SOI-based chip. Simultaneous multi-beam scanning can be realized through peripheral circuit programming control.

Abstract: Among other things, the present disclosure provides oligonucleotides and compositions thereof. In some embodiments, provided oligonucleotides and compositions are useful for adenosine modification. In some embodiments, the present disclosure provides methods for treating various conditions, disorders or diseases that can benefit from adenosine modification.

Abstract: Methods and devices for sensing current through a power converter circuit are presented. According to one aspect, currents through high-/low-side transistors are sensed via respective reduced size replica transistors. According to another aspect, the sensed currents are used to generate bridging currents that are combined with the sensed currents to generate a continuous current sense signal. According to another aspect, the bridging currents include slopes that are generated from slopes of the sensed currents. According to another aspect, the sensed currents are combined and filtered to generate a continuous sense signal. According to another aspect, the continuous current sense signal is a voltage that is compared to a reference voltage to generate a current limit status flag used to control operation of the power converter circuit. According to other aspects, the current sense voltage is used to control ON/OFF duty cycle of the power converter circuit.

Abstract: A method for deep learning video microscopy-based antimicrobial susceptibility testing of a bacterial strain in a sample by acquiring image sequences of individual bacterial cells of the bacterial strain in a subject sample before, during, and after exposure to each antibiotic at different concentrations. The image sequences are compressed into static images while preserving essential phenotypic features. Data representing the static images is input into a pre-trained deep learning (DL) model which generates output data; and antimicrobial susceptibility for the bacterial strain is determined from the output data.

Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.

Abstract: A non-transitory computer-readable medium of a device that stores computer-executable instructions is provided. When the instructions are executed by the device, the instructions cause the device to: determine a line index of a block unit determined from an image frame in the bitstream for selecting one of reference lines; compare the line index with a first predefined value to determine whether a mode flag is included in the bitstream; determine a mode index in the bitstream for directly selecting a prediction mode from a most probable mode (MPM) list when the mode flag is not included in the bitstream; compare the mode flag to a second predefined value when the mode flag is included in the bitstream to determine whether the prediction mode is selected from the MPM list based on the mode index; and reconstruct the block unit based on the selected reference line and the prediction mode.

Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.

Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method further includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and forming a conductive structure over and electrically connected to the thermal control mechanism. The method further includes forming a second dielectric layer over the first dielectric layer and surrounding the conductive structure.

Abstract: The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

Abstract: A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: A flip-chip bonding structure includes a chip and a circuit board, the chip is bonded to the circuit board by bumps. The circuit board includes a light-transmissive substrate, a first circuit group, a second circuit group, a boundary circuit and an identifying member. The boundary circuit is located between the first and second circuit groups and projects a boundary circuit shadow on light-transmissive substrate. The boundary circuit shadow can be recognized according to the identifying member and is provided to identify the boundary between the first and second circuit groups or identify the position of leads with the smallest pitch.

Abstract: Disclosed are a method for measuring the level of muscle relaxation, a device thereof and an apparatus for measuring muscle relaxation, and the method respectively obtains the sampled values of the acceleration and angular velocity of the measurement site via an acceleration sensor and an angular velocity sensor or a speed sensor and an angular velocity sensor, in order to calculate the degree of muscle relaxation according to the sampled values of the acceleration and angular velocity. As the calculated results combine the sampled values of the acceleration and angular velocity of the measurement site, the accuracy of the calculated results is higher. Moreover, the measurement combines an acceleration sensor and an angular velocity sensor or a speed sensor and an angular velocity sensor, so that the apparatus for measuring muscle relaxation can be placed in any position of the measurement site without influencing the accuracy of the measured results.

Abstract: The present invention relates to energy-efficient collaborative method and apparatus for graph processing, wherein the apparatus comprises at least: a dependency path prefetching unit for receiving active vertex information and prefetching an edge of graph partition along a dependency path, starting with an active vertex in a circular queue; and a direct dependency managing unit for converting dependency relationship between head and tail vertices of a core dependency path into direct dependency and managing it in a cache, and updating dependency indexes according to dynamic changes in graph structure during dynamic graph processing, so as to ensure accurate results of graph processing. The accelerator of the present invention is capable of being integrated into a multi-core processor, thereby processing multiple paths on multiple processor kernels with high concurrency, and in turn accelerating dissemination of vertex states in a graph to speed convergence during graph processing.