Patents by Inventor Hung-Hua Lin

Hung-Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190256352
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; receiving a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer; bonding the first dielectric layer with the second dielectric layer; and bonding the first conductive structure with the second conductive structure.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: HUNG-HUA LIN, PING-YIN LIU, KUAN-LIANG LIU, CHIA-SHIUNG TSAI, ALEXANDER KALNITSKY
  • Publication number: 20190248646
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Shang-Ying Tsai, Hung-Hua Lin, Hsin-Ting Huang, Lung Yuan Pan, Jung-Huei Peng, Yao-Te Huang
  • Publication number: 20190241430
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Patent number: 10294098
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Patent number: 10280076
    Abstract: A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Hua Lin, Ping-Yin Liu, Kuan-Liang Liu, Chia-Shiung Tsai, Alexander Kalnitsky
  • Patent number: 10266390
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Hsin-Ting Huang, Lung Yuan Pan, Jung-Huei Peng, Hung-Hua Lin, Yao-Te Huang
  • Publication number: 20190092627
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Application
    Filed: December 27, 2017
    Publication date: March 28, 2019
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Patent number: 10119909
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 10053361
    Abstract: A microelectromechanical systems (MEMS) package includes a eutectic bonding structure free of a native oxide layer and an anti-stiction layer, while also including a MEMS device having a top surface and sidewalls lined with the anti-stiction layer. The MEMS device is arranged within a MEMS substrate having a first eutectic bonding substructure arranged thereon. A cap substrate having a second eutectic bonding substructure arranged thereon is eutectically bonded to the MEMS substrate with a eutectic bond at the interface of the first and second eutectic bonding substructures. The anti-stiction layer lines a top surface and sidewalls of the MEMS device, but not the first and second eutectic bonding substructures. A method for manufacturing the MEMS package and a process system for selective plasma treatment are also provided.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Hung-Hua Lin, Wen-Chuan Tai, Hsiang-Fu Chen
  • Publication number: 20180022602
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Publication number: 20170297902
    Abstract: A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: HUNG-HUA LIN, PING-YIN LIU, KUAN-LIANG LIU, CHIA-SHIUNG TSAI, ALEXANDER KALNITSKY
  • Patent number: 9776852
    Abstract: The present disclosure provides a method for manufacturing a CMOS-MEMS structure. The method includes etching a cavity on a first surface of a cap substrate; bonding the first surface of the cap substrate with a sensing substrate; thinning a second surface of the sensing substrate, the second surface being opposite to a third surface of the sensing substrate bonded to the cap substrate; etching the second surface of the sensing substrate; patterning a portion of the second surface of the sensing substrate to form a plurality of bonding regions; depositing an eutectic metal layer on the plurality of bonding regions; etching a portion of the sensing substrate under the cavity to form a movable element; and bonding the sensing substrate to a CMOS substrate through the eutectic metal layer.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Chih Hsieh, Lee-Chuan Tseng, Hung-Hua Lin
  • Patent number: 9776858
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Patent number: 9741681
    Abstract: An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold a top surface of the substrate stack, and at least one blade configured to be inserted between two adjacent substrates of the substrate stack, wherein the at least one blade has a pointed tip in plan view and has a channel configured to inject air or fluid.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20170217756
    Abstract: The present disclosure provides a method for manufacturing a CMOS-MEMS structure. The method includes etching a cavity on a first surface of a cap substrate; bonding the first surface of the cap substrate with a sensing substrate; thinning a second surface of the sensing substrate, the second surface being opposite to a third surface of the sensing substrate bonded to the cap substrate; etching the second surface of the sensing substrate; patterning a portion of the second surface of the sensing substrate to form a plurality of bonding regions; depositing an eutectic metal layer on the plurality of bonding regions; etching a portion of the sensing substrate under the cavity to form a movable element; and bonding the sensing substrate to a CMOS substrate through the eutectic metal layer.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: YUAN-CHIH HSIEH, LEE-CHUAN TSENG, HUNG-HUA LIN
  • Patent number: 9708179
    Abstract: In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Patent number: 9611141
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Publication number: 20170077062
    Abstract: An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold a top surface of the substrate stack, and at least one blade configured to be inserted between two adjacent substrates of the substrate stack, wherein the at least one blade has a pointed tip in plan view and has a channel configured to inject air or fluid.
    Type: Application
    Filed: November 8, 2016
    Publication date: March 16, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20170004964
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9508586
    Abstract: A method includes receiving a wafer stack having at least two wafers bonded together. At least one blade is inserted between a first wafer of the at least two wafers and a second wafer of the at least two wafers. The blade has a channel configured to inject air or fluid. The first wafer is debonded from the second wafer using the at least one blade. In another embodiment, a detacher having a convex bottom surface is attached to the wafer stack. The first wafer is debonded from the second wafer using the detacher.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai