Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.

Abstract: A memory device includes plural memory cells and control circuitry. Each of the memory cells is capable of storing multi-bit data corresponding to an erase state and plural program states. The control circuitry is configured to divide plural program loops, which are performed to store the multi-bit data in the plural memory cells, into plural program groups and apply different program pulses, which correspond to each of the plural program groups, to the plural memory cells.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: Provided herein is a memory device including a memory block with memory cells to which word lines and bit lines are connected; page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data that is divided into groups according to a number of specific data, and configured to apply a program enable voltage or a program inhibit voltage to the bit lines according to the variable data; and a data pattern manager configured to control the page buffers to convert the original data into the variable data during the program operation.

Abstract: A semiconductor device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on memory cells selected from among the plurality of memory cells. The control logic is configured to control the program operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation.

Abstract: The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.

Abstract: A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.

Abstract: A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

Abstract: Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.

Abstract: A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.

Abstract: A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.

Abstract: A semiconductor memory apparatus includes: a page buffer circuit, a pass/fail determination circuit, and an operation control circuit. The page buffer circuit may include a sensing latch circuit and a data latch circuit. The pass/fail determination circuit determines a pass/fail for a memory cell. The operation control circuit controls a program operation and a program verify operation to be performed on the memory cell.

Abstract: A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array through word lines and bit lines, and suitable for performing one or more program loops on memory cells that are coupled to a selected word line of the word lines, each program loop including a program voltage application operation and a program verification operation; and a program control circuit suitable for controlling the peripheral circuit to decrease a level of a precharge voltage that is applied to the bit lines during the program verification operation when the number of program loops that are performed is greater than a reference number.

Abstract: A memory device may include a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform a program verify operation for a target program state among a plurality of program states on selected memory cells among the plurality of memory cells. The control logic is configured to control the peripheral circuit to precharge bit lines coupled to first memory cells among the selected memory cells and bit lines coupled to second memory cells among the selected memory cells in the program verify operation. The first memory cells are program-passed memory cells among memory cells programmed to a program state higher than the target program state among the plurality of program states. The second memory cells are memory cells programmed to a program state lower than or equal to the target program state among the plurality of program states.

Abstract: A semiconductor memory device may include a memory cell array circuit and a word line driving circuit. The memory cell array circuit may be connected with a plurality of word lines to store data in a program operation. The word line driving circuit may drive a selected word line among the word lines using a program voltage in the program operation. The word line driving circuit may drive each of non-selected word lines adjacent to the selected word line using a step pass voltage including at least two step voltages.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a control logic circuit configured to control the peripheral circuit so that the program operation is performed. The control logic circuit controls a peripheral circuit so that memory cells to be programmed to first to (N?1)-th program states are programmed in a double program method using a main verify voltage and a sub verify voltage less than the main verify voltage during a verify operation and memory cells to be programmed to the N-th program state are programmed in a normal program method using the main verify voltage during the verify operation, when the verify operation of the memory cells corresponding to the (N?1)-th program state has failed.

Abstract: A memory device including a plurality of memory cells, a threshold voltage distribution measurement component configured to measure a threshold voltage distribution of a first read operation of sensing data from programmed memory cells among the plurality of memory cells, and a threshold voltage distribution of a second read operation of sensing the data from the programmed memory cells and outputting the data to an outside, a distribution shift compensation table generator configured to calculate a shift direction and a shift distance based on a result of comparing the threshold voltage distribution of the first read operation and the threshold voltage distribution of the second read operation, and generate a distribution shift compensation table based on the shift direction and the shift distance, and a read operation controller configured to perform a third read operation on target memory cells based on the distribution shift compensation table.

Abstract: A page buffer circuit includes a sensing latch circuit and a caching latch circuit. The sensing latch circuit is configured to receive and sense data that is stored in a memory cell during a normal read operation. The caching latch circuit is configured to receive and sense the data that is stored in the memory cell during a suspend read operation.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: Disclosed is a method of manufacturing an epitaxy oxide thin film of enhanced crystalline quality, and an epitaxy oxide thin film manufactured thereby according to the present invention. With respect to the manufacturing method of the epitaxy oxide thin film, which epitaxially grows an orientation film with an oxide capable of being oriented to (001), (110), and (111) on a single crystal Si substrate, because time required for raising a temperature of the orientation film up to an annealing temperature at room temperature is extremely minimized, thermal stress arising from the large difference in thermal expansion coefficients between the substrate and the orientation film is controlled, so crystalline quality of the epitaxy oxide thin film can be enhanced. Moreover, various epitaxial functional oxides are integrated into the thin film of enhanced crystalline quality so that a novel electronic device can be embodied.