Abstract: A memory device includes a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit programs the plurality of memory cells to a program state among a plurality of program states. The control logic controls the peripheral circuit to perform a program verify operation for at least one program state among the plurality of program states, counts a bit number having a predetermined logic value by comparing a program verify voltage corresponding to a target program state in the at least one program state in a program verify operation for the target program state with threshold voltages of the plurality of memory cells, and determines a start time of a program verify operation for a program state higher than the target program state among the plurality of program states, based on the bit number having the predetermined logic value.

Abstract: A semiconductor memory device includes a memory block, and control logic. The memory block includes a plurality of memory cells. The control logic controls a peripheral circuit to perform a read operation on selected memory cells among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period of the bit line precharge operation, in which a voltage of a plurality of bit lines coupled to the memory block increases.

Abstract: A page buffer circuit includes an intermediate circuit, a data storage circuit and an enhancive circuit. The intermediate circuit is coupled to a bit line coupled to a memory region and configured to form apply a voltage having a voltage level, corresponding to a status of the memory region, to a sensing node. The data storage circuit is configured to store, therein, a value that corresponds to the status of the memory region in response to the voltage level. The enhancive circuit is coupled to the sensing node and configured to increase a capacitance of the sensing node in an enhancive interval during a selected operation.

Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.

Abstract: An operating method of a non-volatile memory device comprises: performing a foggy operation applying a first application voltage to a word line and applying a first verification voltage having a same level as or a higher level than a target threshold voltage to the word line, determining whether the foggy operation is completely performed according to whether a number of memory cells each having a threshold voltage higher than the first verification voltage is equal to or greater than a first number, performing a fine operation applying a second application voltage to the word line and applying a second verification voltage having the same level as the target threshold voltage, and determining whether the fine operation is completely performed, according to whether a number of memory cells each having a threshold voltage lower than the second verification voltage is less than or equal to a second number.

Abstract: A nonvolatile memory device includes: a peripheral circuit for repeatedly performing program loops each including a program operation including a setup operation on the plurality of bit lines and an application operation of applying a program pulse to a selected word line and the verification operation, and a control logic circuit for controlling the peripheral circuit, wherein the peripheral circuit performs a first program loop of the program loops by: applying each a first and a second program pulses in each a first and a second section of the application operation, setting a first bit line to a first level and a second bit line to a second level lower than the first level from a start of the setup operation until an end of the first section, and resetting the first and the second bit line to the second level in the second section.

Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.

Abstract: A semiconductor memory device includes a memory cell array circuit and a driving force adjustment circuit. The memory cell array circuit includes a plurality of memory cells. The driving force adjustment circuit adjusts driving forces of a plurality of respective verify pass voltages based on whether or not the plurality of memory cells are programmed.

Abstract: A self-power wireless switch according to an embodiment of the present invention includes a lower body, an upper body rotatably coupled, through a rotating shaft, to one side of the lower body; a switch cover rotatably coupled to one side of the lower body, or rotatably coupled to one side of an upper cover, a switch member capable of contacting the switch cover, a printed circuit board (PCB) comprising a contact unit which may contact the switch member that has been pressed by a user, and a generator positioned at the lower surface of the PCB and supplying power to the PCB. When the user presses the switch cover, the upper body rotates, and pressure is applied to a generator bar formed on the generator, and thus power is generated.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of program loops, each including a program voltage application operation of applying a program voltage to a selected memory cell and a verify operation of verifying a program state of the selected memory cell, and a control logic configured to control, at the program voltage application operation, the peripheral circuit to apply a precharge voltage to the common source line and change at least one of a magnitude of the precharge voltage and a time during which the precharge voltage is applied, depending on a magnitude of the program voltage.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: Provided herein may be a memory device, a method of operating the same and a page buffer. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be coupled to the plurality of memory cells through a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.

Abstract: A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.

Abstract: There are provided a semiconductor memory device and a method for operating the same. The semiconductor memory device includes: a memory cell array with a plurality of memory cells programmed to a plurality of program states; a peripheral circuit configured for performing a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit for determining a verify result of each of the plurality of program states by performing an individual state current sensing operation on the selected memory cells among the memory cells; and a control logic for controlling the current sensing circuit to perform the individual state current sensing operation, based on a number of program loops, among a plurality of program loops, that are performed.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation and a read operation on the memory cell array. The control logic is configured to control an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform an SLC program operation on memory cells included in a selected page among the plurality of memory cells, compares the number of first fail bits counted by performing a normal sensing operation on the selected page and the number of second fail bits counted by performing a multi-sensing operation on the selected page, and corrects at least one evaluation time to be used for a read operation based on a result of the comparison.

Abstract: The present technology relates to an electronic device. A memory device that reduces noise generated during a sensing operation includes a plurality of pages, each including a plurality of memory cells, a peripheral circuit configured to sense a selected page among the plurality of pages, the selected page including a selected memory cell and a sensing node controller configured to control, based on a result of a first sensing operation among a plurality of sensing operations that are performed to sense a logical page among a plurality of logical pages in the selected page, a sensing node in a page buffer coupled to the selected memory cell through a bit line during a second sensing operation.

Abstract: A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: A memory device and an operating method thereof are provided. The memory device includes a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data, a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal, a cache latch configured to receive the read data through the page bus line and temporarily store the read data, and a pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time.