Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Abstract: A semiconductor memory device may include a caching latch circuit and a sensing latch circuit. The caching latch circuit may store setup data. The sensing latch circuit may store sensing data.

Abstract: A memory device includes a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit programs the plurality of memory cells to a program state among a plurality of program states. The control logic controls the peripheral circuit to perform a program verify operation for at least one program state among the plurality of program states, counts a bit number having a predetermined logic value by comparing a program verify voltage corresponding to a target program state in the at least one program state in a program verify operation for the target program state with threshold voltages of the plurality of memory cells, and determines a start time of a program verify operation for a program state higher than the target program state among the plurality of program states, based on the bit number having the predetermined logic value.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.

Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

Abstract: Provided herein is a memory device including a memory block with memory cells to which word lines and bit lines are connected; page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data that is divided into groups according to a number of specific data, and configured to apply a program enable voltage or a program inhibit voltage to the bit lines according to the variable data; and a data pattern manager configured to control the page buffers to convert the original data into the variable data during the program operation.

Abstract: Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.

Abstract: A semiconductor memory device includes a memory block, and control logic. The memory block includes a plurality of memory cells. The control logic controls a peripheral circuit to perform a read operation on selected memory cells among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period of the bit line precharge operation, in which a voltage of a plurality of bit lines coupled to the memory block increases.

Abstract: A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation and a read operation on the memory cell array. The control logic is configured to control an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform an SLC program operation on memory cells included in a selected page among the plurality of memory cells, compares the number of first fail bits counted by performing a normal sensing operation on the selected page and second fail bits counted by performing a multi-sensing operation on the selected page, and corrects at least one evaluation time to be used for a read operation based on a result of the comparison.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Abstract: A memory device including a plurality of memory cells, a threshold voltage distribution measurement component configured to measure a threshold voltage distribution of a first read operation of sensing data from programmed memory cells among the plurality of memory cells, and a threshold voltage distribution of a second read operation of sensing the data from the programmed memory cells and outputting the data to an outside, a distribution shift compensation table generator configured to calculate a shift direction and a shift distance based on a result of comparing the threshold voltage distribution of the first read operation and the threshold voltage distribution of the second read operation, and generate a distribution shift compensation table based on the shift direction and the shift distance, and a read operation controller configured to perform a third read operation on target memory cells based on the distribution shift compensation table.

Abstract: The present disclosure relates to a memory device may include a plurality of memory cells coupled to a selected word line and to be programmed to one of first to n-th program states distinguished from each other based on threshold voltages thereof, a sensing latch storing data sensed from a bit line coupled to one memory cell, a pre-latch storing pre-verify information and a plurality of data latches storing data to be stored in the one memory cell, wherein at least one data latch stores main verify information on the main verify voltage during verify operations for the first program state to a threshold program state among the first to n-th program states until the verify operation for the threshold program state passes, and wherein the pre-latch stores the main verify information on the n-th program state after the verify operation for the threshold program state passes.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a current sensing circuit configured to perform an individual current sensing operation according to a verify result of each of selected program states in an individual current sensing mode and perform an entire current sensing operation according to a verify result of the entire memory cells regardless of the selected program states after the individual current sensing operation is performed in a mixed current sensing mode, and a voltage generator configured to apply a program voltage to a selected word line connected to the memory cells during a first amount of time in the individual current sensing mode and apply the program voltage to the selected word line during a second amount of time greater than the first amount of time in the mixed current sensing mode, in response to the operation code.

Abstract: The present technology relates to an electronic device. A memory device that reduces noise generated during a sensing operation includes a plurality of pages, each including a plurality of memory cells, a peripheral circuit configured to sense a selected page among the plurality of pages, the selected page including a selected memory cell and a sensing node controller configured to control, based on a result of a first sensing operation among a plurality of sensing operations that are performed to sense a logical page among a plurality of logical pages in the selected page, a sensing node in a page buffer coupled to the selected memory cell through a bit line during a second sensing operation.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including memory cells, a peripheral circuit configured to perform a plurality of program loops to cause a threshold voltage of selected memory cells included in a selected page among the memory cells to attain a target voltage, and a control logic circuit configured to control the peripheral circuit to perform the program loops by selectively applying a normal program or a double program to the program loops.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.