Abstract: A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include a memory block coupled to bit lines and word lines, a voltage generator configured to apply at least one of a program voltage or a verify voltage to a word line selected from among the word lines, page buffers configured to precharge less than all or all of the bit lines during a verify operation performed on the memory cells, an operation logic configured to output verify information related to a verify operation performed during a program operation in response to a command, and a page buffer controller configured to output page buffer control signals so that the less than all of the bit lines are selectively precharged or the all of the bit lines are precharged depending on the verify information.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device Includes a control logic circuit configured to control the peripheral circuit so that the program operation is performed. The control logic circuit controls a peripheral circuit so that memory cells to be programmed to first to (N?1)-th program states are programmed in a double program method using a main verify voltage and a sub verify voltage less than the main verify voltage during a verify operation and memory cells to be programmed to the N-th program state are programmed in a normal program method using the main verify voltage during the verify operation, when the verify operation of the memory cells corresponding to the (N?1)-th program state has failed.

Abstract: A memory device may include a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform a program verify operation for a target program state among a plurality of program states on selected memory cells among the plurality of memory cells. The control logic is configured to control the peripheral circuit to precharge bit lines coupled to first memory cells among the selected memory cells and bit lines coupled to second memory cells among the selected memory cells in the program verify operation. The first memory cells are program-passed memory cells among memory cells programmed to a program state higher than the target program state among the plurality of program states. The second memory cells are memory cells programmed to a program state lower than or equal to the target program state among the plurality of program states.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.

Abstract: The present technology includes memory device and a method of operating the same. The memory device includes a current sensing circuit configured to perform an individual current sensing operation according to a verify result of each of selected program states in an individual current sensing mode and perform an entire current sensing operation according to a verify result of the entire memory cells regardless of the selected program states after the individual current sensing operation is performed in a mixed current sensing mode, and a voltage generator configured to apply a program voltage to a selected word line connected to the memory cells during a first amount of time in the individual current sensing mode and apply the program voltage to the selected word line during a second amount of time greater than the first amount of time in the mixed current sensing mode, in response to the operation code.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be coupled to the plurality of memory cells through a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.

Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.

Abstract: An electronic device is provided. A page buffer includes at least one data latch, a sensing latch, and a bit line voltage controller. At least one data latch stores a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell. The sensing latch stores a program verification result of a current program loop among the plurality of program loops. The bit line voltage controller updates the program verification result of the previous program loop which is stored in the at least one data latch to the sensing latch during a program operation of a next program loop of the current program loop among the plurality of program loops.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

Abstract: A memory device and an operating method thereof are provided. The memory device includes a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data, a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal, a cache latch configured to receive the read data through the page bus line and temporarily store the read data, and a pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include a memory block coupled to bit lines and word lines, a voltage generator configured to apply at least one of a program voltage or a verify voltage to a word line selected from among the word lines, page buffers configured to precharge less than all or all of the bit lines during a verify operation performed on the memory cells, an operation logic configured to output verify information related to a verify operation performed during a program operation in response to a command, and a page buffer controller configured to output page buffer control signals so that the less than all of the bit lines are selectively precharged or the all of the bit lines are precharged depending on the verify information.

Abstract: The present technology relates to a page buffer and a semiconductor memory device with the same. The page buffer includes a bit line controller connected to a bit line and configured to control a potential level of a sensing node based on a current level of the bit line during a sensing operation, and a main latch configured to latch data based on a potential of the sensing node. The bit line controller includes a first transistor connected between the bit line and a common sensing node, and a second transistor connected between a power voltage terminal and the common sensing node, and the second transistor is a PMOS transistor.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a string having a plurality of memory cells in which data is stored, and a page buffer coupled to the string through a bit line and configured to precharge the bit line, or sense voltage or current of the bit line. The page buffer may include a first switch configured to transfer the voltage of the bit line to a common sensing node in response to a page buffer sensing signal, a second switch configured to transfer a supply voltage to the common sensing node in response to a common sensing signal, and a third switch configured to couple the common sensing node to a latch in response to a sensing signal and adjust voltage of the common sensing node depending on a voltage level of the sensing signal.

Abstract: The present disclosure relates to a memory device may include a plurality of memory cells coupled to a selected word line and to be programmed to one of first to n-th program states distinguished from each other based on threshold voltages thereof, a sensing latch storing data sensed from a bit line coupled to one memory cell, a pre-latch storing pre-verify information and a plurality of data latches storing data to be stored in the one memory cell, wherein at least one data latch stores main verify information on the main verify voltage during verify operations for the first program state to a threshold program state among the first to n-th program states until the verify operation for the threshold program state passes, and wherein the pre-latch stores the main verify information on the n-th program state after the verify operation for the threshold program state passes.