Abstract: Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.

Abstract: This disclosure relates to an apparatus including a zone manager to manage memory allocation and behavior under a Zoned Namespaces (ZNS) implementation. The zone manager may include a monitor circuit, an evaluation circuit, and a signaling circuit. The monitor circuit is configured to monitor a zone metric for each zone of a non-volatile storage device. The evaluation circuit is configured to determine health for each zone based on the zone metric. The signaling circuit is configured to notify a host of the zone health for one or more zones in response to the zone metric for the zone(s) satisfying an alert threshold.

Abstract: Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.

Abstract: A non-volatile storage apparatus comprises a non-volatile storage and a control circuit connected to the non-volatile storage. The non-volatile storage structure is organized into multiple partitions. Each partition is preassigned to a different data shaping level. Data to be stored in the non-volatile storage is shaped based on its entropy. The control circuit is configured to write shaped data to a partition of the multiple partitions that is preassigned to a same shaping level as the shaped data.

Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.

Abstract: Calibrating read reference voltages is disclosed. In an aspect, a control die calibrates read reference voltages for reading the non-volatile memory cells. The control die is bonded to a memory die that contains memory cells. In one aspect, a tiered approach to calibrating read reference voltages is taken. For example, first the control die may attempt to determine new values for read reference voltages. If the new read reference voltages are satisfactory, then the control die may use the new read reference voltages. The control die could use one or more different techniques to determine new read reference voltages. If the new read reference voltages determined by the control die are unsatisfactory, then a memory controller in communication with the control die may calibrate the read reference voltages. By the control die determining the new read reference voltages, the memory controller is substantially less burdened with such tasks.

Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: Enhanced error correction for data stored in storage devices are presented herein. An error correction circuit decodes an encoded data segment retrieved from a storage media. This decode uses a selected error correction scheme having an error correction limit. The error correction circuit tracks a number of bit corrections made to the encoded data segment during decode. A detection circuit sends a redundant version of the encoded data segment to the error correction circuit in response to the number of bit corrections satisfying a threshold limit set below the error correction limit to mitigate undetected errors in decoding the encoded data segment. An output circuit can transfer resultant data decoded by the error correction circuit to other systems, such as a host device.

Abstract: In one embodiment, the disclosure teaches an apparatus including a memory array and a processor in communication with the memory array. The processor is configured to determine health scores of blocks of the memory array, where the health scores indicate the health of the blocks. The processor also is configured to receive data from a host, and select an interleaving scheme for programming the data based on the data type and a block to which the data is written based on the health scores. In one embodiment, sequential type data is written to unhealthy blocks and non-sequential data is written to healthy blocks.

Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.

Abstract: A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.

Abstract: A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: A controller for a phase change memory forms a dedicated burst write partition in the phase change memory and initializes memory cells of the dedicated burst write partition to a SET state. Programming of selected memory cells in the dedicated burst write partition is carried out using only RESET pulses.

Abstract: Disclosed herein is a memory device and a method of descrambling and decoding encoded data. In one aspect, encoded data is received. A scrambling seed is obtained from the encoded data prior to decoding the encoded data. The encoded data is descrambled according to the scrambling seed, and the descrambled data is decoded. The descrambled data may be decoded according to statistics of the descrambled data.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length sequence of prior read commands are generated and compared to a read command history datastore. When a prior pattern of read commands is found corresponding to the search sequence, a next read command that previously followed that search sequence may be used as a predicted next read command and data pre-fetched based on the read command data location information associated with that prior read command that is being used as the predicted read command.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.