Abstract: Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used.

Abstract: A method and apparatus for baking a film onto a substrate. A film, such as a layer of photoresist, is disposed on a first surface of a substrate while a second surface is exposed to a liquid bath. The liquid bath is maintained at a pre-selected temperature. Exposure of the substrate to the liquid bath allows the film on the opposite surface to bake. The liquid bath is then re-circulated to maintain a constant and uniform temperature gradient across the substrate.

Abstract: A method and apparatus for baking a film onto a substrate. A film, such as a layer of photoresist, is disposed on a first surface of a substrate while a second surface is exposed to a liquid bath. The liquid bath is maintained at a pre-selected temperature. Exposure of the substrate to the liquid bath allows the film on the opposite surface to bake. The liquid bath is then re-circulated to maintain a constant and uniform temperature gradient across the substrate.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A phase shifting mask can be used to form features on a semiconductor wafer with exposure lights of two different wavelengths. The depth of the phase shifting layer is calculated and fabricated such that it shifts a first exposure light about 180° and a second exposure light about 180°.

Abstract: A method and apparatus for baking a film onto a substrate. A film, such as a layer of photoresist, is disposed on a first surface of a substrate while a second surface is exposed to a liquid bath. The liquid bath is maintained at a pre-selected temperature. Exposure of the substrate to the liquid bath allows the film on the opposite surface to bake. The liquid bath is then re-circulated to maintain a constant and uniform temperature gradient across the substrate.

Abstract: Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, Si—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.

Abstract: The invention encompasses a method for forming a pattern across an expanse of photoresist. The expanse comprises a defined first region, second region and third region. The first region is exposed to a first radiation while leaving the third region not exposed; and subsequently the second region is exposed to a second radiation while leaving the third region not exposed to the second radiation. The second radiation is different from the first radiation. The exposure of the first and second regions of the expanse to the first and second radiations alters the solubility of the first and second regions in a solvent relative to the solubility of the third region of the expanse. After the first and second regions of the expanse are exposed to the first and second radiations, the expanse is exposed to a solvent to pattern the expanse. The invention can be utilized in forming radiation-patterning tools and stencils; and in pattering semiconductor substrates.

Abstract: Structures and methods are provided for shielding field emitter devices from radiation. In an embodiment, a shielding layer inhibits radiation from degrading field emitter devices while exerting a predetermined force upon the field emitter devices so as to restrain from damaging the structure or affecting performance of the devices. In an embodiment, the field emitter under the protection of the shielding layer sustains structural equilibrium. In an embodiment, the field emitter sustains structural elasticity. In an embodiment, the shielding layer is comprised of tetratantalum boride, which inhibits radiation from degrading field emitter devices while exerting a predetermined force upon the field emitter devices so as to restrain from damaging the structure or affecting performance of the devices. In other embodiments, the field emitter under the protection of the tetratantalum boride layer sustains structural equilibrium or structural elasticity.

Abstract: A method for wet processing of a semiconductor-containing substrate that reduces contamination in the wet process by removing undesired sources of gas contamination, the method comprising: pumping a processing liquid through a degasifier, exposing the semiconductor wafer, in a vessel, to the degasified processing liquid; and optionally recirculating the processing liquid through the degasifier and back into the vessel.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or,ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer.

Abstract: An improved method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is then deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed of the substrate is optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be used after deposition of a metal layer, or at other process steps as desired.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: In one aspect, the invention includes a method of maintaining dimensions of an opening in a semiconductive material stencil mask comprising providing two different dopants within a periphery of the opening, the dopants each being provided to a concentration of at least about 1017 atoms/cm3.

Abstract: Structures and methods are provided for shielding field emitter devices from radiation. In one exemplary embodiment, a shielding layer inhibits radiation from degrading field emitter devices while exerting a predetermined force upon the field emitter devices so as to restrain from damaging the structure of the devices or affect the devices' electronic or electrical performance. In another exemplary embodiment, the field emitter under the protection of the shielding layer is capable of sustaining structural equilibrium. In yet another embodiment, the field emitter is capable of sustaining structural elasticity.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.