Abstract: The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely-spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filed with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as rouglness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used.

Abstract: There are provided methods of making hardmask assemblies or other layered structures, and other masks, including providing an annular seal member between a first surface of layered structure, preferably a hardmask assembly, and a firs clamp element, the hardmask assembly comprising at least a hardmask layer; and applying a force between the first clamp element and a second clamp element to hold the hardmask assembly between the annular seal member and the second clamp element In addition, there are provided methods further comprising etching the first surface of the hardmask assembly within the bounds of an interior space defined by the annular seal member. Furthermore, there are provided methods further comprising etching the substrate layer through the hardmask layer and/or removing the hardmask layer after etching the substrate layer.

Abstract: A semiconductor processing method of promoting adhesion of photoresist to an outer substrate layer predominately comprising silicon nitride includes, a) providing a substrate; b) providing an outer layer of Si3N4 outwardly of the substrate, the outer Si3N4 layer having an outer surface; c) covering the outer Si3N4 surface with a discrete photoresist adhesion layer; and d) depositing a layer of photoresist over the outer Si3N4 surface having the intermediate discrete adhesion layer thereover, the photoresist adhering to the Si3N4 layer with a greater degree of adhesion than would otherwise occur if the intermediate discrete adhesion layer were not present.

Abstract: The invention encompasses a method for forming a pattern across an expanse of photoresist. The expanse comprises a defined first region, second region and third region. The first region is exposed to a first radiation while leaving the third region not exposed; and subsequently the second region is exposed to a second radiation while leaving the third region not exposed to the second radiation. The second radiation is different from the first radiation. The exposure of the first and second regions of the expanse to the first and second radiations alters the solubility of the first and second regions in a solvent relative to the solubility of the third region of the expanse. After the first and second regions of the expanse are exposed to the first and second radiations, the expanse is exposed to a solvent to pattern the expanse. The invention can be utilized in forming radiation-patterning tools and stencils; and in pattering semiconductor substrates.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used.

Abstract: In but one implementation in the fabrication of a phase shift mask, both process alignment in the formation of a phase shift alignment region and degree of phase shift of the phase shift alignment region is determined at least in part by using aerial image measurement equipment. In one implementation, aerial image measurement equipment is used to both determine phase shift of a phase shift alignment region at least in part by capturing a series of aerial images as a function of focus and to determine process alignment in the formation of the phase shift alignment region at least in part by measuring distance between spaced low intensity locations defined by an edge of the phase shift alignment region and an adjacent alignment feature edge.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: In one aspect, the invention encompasses an apparatus for semiconductor processing comprising: a) at least one support member comprising an upper surface for supporting a semiconductor wafer; b) a component through which the support member extends, the component comprising a front surface and a back surface, at least one of the support member and the component being movable relative to the other of the support member and the component such that the support member can support a wafer in an elevated position above the front surface and can be withdrawn into the component to lower the wafer relative to the front surface of the component; and c) a block joined to the support member below the component back surface, the block engaging the component back surface when the support member upper surface extends above the component to a predetermined distance, the block preventing the support member upper surface from extending beyond the front surface by more than the predetermined distance.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: Methods of making hardmask assemblies or other layered structures, and other masks, include providing an annular seal member between a first surface of layered structure, preferably a hardmask assembly, and a first clamp element, the hardmask assembly comprising at least a hardmask layer; and applying a force between the first clamp element and a second clamp element to hold the hardmask assembly between the annular seal member and the second clamp element. In addition, there are provided methods further comprising etching the first surface of the hardmask assembly within the bounds of an interior space defined by the annular seal member. Methods further comprise etching the substrate layer through the hardmask layer and/or removing the hardmask layer after etching the substrate layer.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.