Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or predetermined, rate of voltage change.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations. In an embodiment, a waveform is received, delayed, and output to an output terminal using at least one relatively low-power device. Supplemental output power is provided by at least one relatively high-power device until the output waveform exceeds a threshold.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current.

Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. In an embodiment, rising and/or falling edge slopes are monitored. For example, a dV/dt may be monitored. The dV/dt can be monitored by coupling a capacitance to the output signal, generating a current with the capacitance, and generating a voltage from the current. The voltage is generally proportional to the dV/dt. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.

Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Abstract: Methods and systems for controlling delay relatively independent of process, supply-voltage, and/or temperature (“PVT”) variations include sensing an output signal after a number of inverters and activating different numbers of transistors and/or adjusting strength of transistors in a delay path to compensate for PVT variations.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. The invention generates interim voltages when a voltage difference between terminals exceeds one or more thresholds. For example, in an embodiment, the present invention monitors voltages at first and second terminals of a circuit and provides an interim voltage to the second terminal when the voltage at the first terminal pad exceeds a first threshold and a voltage at the second terminal is below a second threshold. In other words, when a first power supply is powered on before a second power supply is powered on. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, e.g., until the second power supply is powered on.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequence currents, including methods and systems for biasing transistors in paths susceptible to power-on sequence damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on. In an embodiment, the invention is applied to a circuit having a first and second IC terminals coupled to a first and second power supplies, respectively. The invention protects the circuit in the event that the first power supply is powered-on before the second power supply is powered-on. The method includes sensing voltage amplitudes from the first and second power supplies. When first power supply is powered-on before the second power supply is powered-on, the first IC terminal is coupled to the second IC terminal. The substantially prevents undesired power-on sequence currents from flowing between the first and second IC terminals.

Abstract: Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.