Abstract: Methods and systems for maintaining desired circuit and/or signal characteristics, such as impedance matching characteristics and rise and fall time characteristics, over a range of PVT variations. In an embodiment, a PVT compensating circuit senses one or more circuit and/or signal characteristics at an output pad or terminal. When the one or more circuit and/or signal characteristics are affected by PVT variations in the IC and/or load, the PVT compensating circuit controls a variable output drive to maintain the one or more circuit and/or signal characteristics within a desired or predetermined range. The PVT compensating circuit is designed to compensate over a range of PVT variations. In an embodiment, the PVT compensating circuit senses a rate of voltage change over time (i.e., dV/dt), of an output signal at the output terminal. During state transitions of the output signal, the output signal is adjusted as needed to maintain a desired, or predetermined, rate of voltage change.

Abstract: A method of preventing Hot Carrier Injection in input/output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can tolerate. By placing input/output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. A circuit for preventing Hot Carrier Injection in these input/output devices comprises comparing an input voltage to a reference voltage, and if conditions that would produce Hot Carrier Injection are present (e.g. when input voltage is greater than reference voltage), slowing the turn-on of one of the series connected input/output devices, thereby reducing the voltage from the drain-to-source of another series connected input/output device.

Abstract: A system and method for level shifting a core, lower voltage in a one-stage level shift device to produce a higher, driving voltage. The system includes a first device that optimally functions with a first voltage and that outputs the first voltage. The system also includes a one-stage level shift device that receives the first voltage and shifts the first voltage to a second voltage without an intermediate voltage, the second voltage being higher than the first voltage. The system also includes a second device that receives the second voltage to optimally function. In some cases, the first voltage can be a periodic wave such that the higher voltage is produced with one portion of the level shift device during a first portion of the wave and another portion of the level shift device during a second portion of the wave.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Abstract: The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: The present invention provides an integrated circuit driver having multiple resistance paths that switch on at different stages of the rising and falling transitions of the driver's output signal waveform. The driver also has a control circuit configured to turn on the one or more resistance paths during at least one predetermined stage of the output signal during transitions, thus reducing the control circuit's effective resistance to control the slope of the transitions during the predetermined stage.

Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.

Abstract: The present invention provides a buffer circuit that can tolerate over-voltage, and a method for protecting buffer circuits from over-voltage. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V). In a preferred embodiment, the buffer circuit has a pre-driver circuit having a pull-up circuit coupled to an interface node via a PMOS switch transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the input voltage source when an input voltage at the interface node exceeds the VDD voltage by a threshold voltage. The buffer circuit has a first biasing transistor that ties an N-well of the integrated circuit to the VDD voltage source when a control node of a PMOS driver transistor is in a first logic state, and a second biasing transistor that ties the N-well to the VDD voltage source when the control node of the PMOS driver transistor is in a second logic state.

Abstract: The present invention provides a buffer circuit that consumes little power. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V) at an interface node. In a preferred embodiment, the buffer circuit has a driver PMOS transistor, and a pre-driver circuit having a pull-up circuit coupled to the interface node via a PMOS switch transistor and a first PMOS pass transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the interface node when an input voltage at the interface node exceeds the VDD voltage by a PMOS threshold voltage.

Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Abstract: Emitter-switched transistor structures are described which have only three terminals. A part of the drain current is used to provide the base current of an emitter-switched NPN transistor and to concurrently cause the injection of holes to conductivity-modulate the emitter-switching MOSFET of the NPN transistor. The reduced on-resistance of the emitter-switching MOSFET causes the emitter-switched NPN transistor to inject more electrons, which in turn leads to more hole injection via a positive feedback mechanism, resulting in a low on-state voltage drop for the device. In another embodiment of the invention, a thyristor structure is provided with the anode switched by a high-voltage MOSFET. Yet another embodiment of the invention provides a four terminal bidirectional device with no diffusions required on the backside of the wafer.