Abstract: A semiconductor device structure having an epitaxial layer, formed of silicon for example, is disposed on a high band-gap material, such as silicon carbide, which is in turn disposed on a semiconductor substrate, such as silicon. The high band gap material achieves a charge concentration much higher than that of a conventional semiconductor material for the same breakdown voltage.

Abstract: An insulated gate base resistance controlled thyristor with a high controllable current capability is described. The device has a high density of MOS-channels modulating the resistance of the base region of the NPN transistor of the thyristor structure. The higher MOS channel density is achieved by contacting directly only the N.sup.++ emitter and the P.sup.+ cells (and not the P base region of the NPN transistor) to the cathode electrode. The N.sup.++ cells (i.e. the P base regions each containing an N.sup.++ emitter) and the P.sup.+ cells are connected in certain regions under the MOS gate by a P.sup.- region to provide a higher base resistance when a positive bias is applied to the MOS gate, thereby facilitating latching of the thyristor. The added MOS gate controlled base resistance between cells allows the P base cells to be designed with smaller dimensions for high maximum controllable current without affecting latch-up capability.

Abstract: A process for forming a MOS gated device in which an oxide layer grown on a silicon surface is first patterned to form windows for implantation of P++ regions. Following implantation of the P++ regions, the oxide is completely etched off, and a thermal oxide layer is grown on the wafer surface. Since oxide grows thicker over the highly doped P++ region, the result is a pattern of thick and thin oxide layers atop the silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms significantly penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the P type base regions previously formed.

Abstract: A thyristor structure in which the DMOSFET connecting the N.sup.+ emitter to the N.sup.- drift region is eliminated and instead replaced with a DMOSFET connecting the N.sup.+ cathode to the N- drift region providing the base drive for the PNP transistor of the thyristor structure. The thyristor structure of the present invention provides lower on-state voltage drop as compared to prior art EST structures.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.

Abstract: MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N.sup.+ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N.sup.+ emitter, the potential of the N.sup.+ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P.sup.+ cathode is such that punch-through occurs in these regions.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn-on and turn-off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel.

Abstract: A MOS-gated power semiconductor device which combines bipolar conduction with MOS-gate control to achieve low on-state voltage drop while having fast-switching characteristics. A floating P injector region located at the upper surface of the device injects holes, and a grounded P collector region, also located at the upper surface of the device, collects the injected holes. A driver DMOSFET integrated in the structure couples the P injector region to the drain potential during the on-state of the device. The P collector region is configured in such that the driver DMOSFET is conductivity modulated by a positive feedback mechanism, thereby drastically reducing the on-resistance of the device at high current levels.

Abstract: A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability. In another embodiment, forward blocking is achieved by depletion from the trench gates and a junction depletion from a P diffusion between the gates. Both embodiments are preferably fabricated in a cellular geometry. The device may also be provided in a horizontal conduction configuration in which the MOS gate is disposed on the upper surface of the semiconductor wafer over the deep-depletion region.

Abstract: A termination structure for a MOSgated device uses a plurality of series-connected lateral P-MOS devices extending in series, from source to drain of the main device. The P-MOS devices are formed in ring fashion around the periphery of the area being terminated. A plurality of concentric spaced P rings diffused into an N type chip termination area are covered by the main device gate oxide which is, in turn, covered with conductive polysilicon to act as a gate for the P-MOS devices so formed. The innermost P ring of each pair of P rings is connected to its gate to prevent turn on of the N channel device. The breakdown voltage of the termination is the sum of the threshold voltage of the P-MOS transistors. A zener diode can be added to the chain to increase the breakdown voltage of the termination.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. In some embodiments, the device has two gate drives and is a four terminal device. In other embodiments, the device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: A bidirectional thyristor structure with a single MOS gate controlled turn off capability. In a vertical conduction embodiment, the device has a six layer structure including a backside diffusion. One vertical conduction structure includes a single body region at the first surface of the device for conduction in both the forward and reverse directions. Another vertical conduction structure includes a two body regions at the first surface, one for controlling forward conduction and the other for controlling reverse conduction. The vertical conduction embodiments are preferably implemented in a cellular geometry, with a large number of symmetrical cells connected in parallel. The bidirectional thyristor of the present invention can also be provided in a lateral conduction structure for power IC applications.

Abstract: A process for forming a MOS gated device in which an oxide layer is patterned to have adjacent thick and thin oxide layers atop a silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the base regions previously formed. A contact opening mask which is critically aligned to the polysilicon mask forms openings for making contact to the silicon. The device is completed using non-critical alignment masking steps.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. The device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.