Abstract: Disclosed is a radio frequency (RF) filter that vertically integrates an acoustic die with inductors formed in one or more layers above the acoustic die. The acoustic die may be over-molded so that the acoustic dome, important for maintaining acoustic integrity, may be protected.

Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

Abstract: Disclosed are devices having a metal-insulator-metal (MIM) capacitor and methods for fabricating the devices. The MIM capacitor includes a plurality of trenches in a Silicon (Si) substrate; a porous Si surface formed in the plurality of trenches, where the porous Si surface has an irregular surface on sidewalls and bottoms of the plurality of trenches; an oxide layer conformally disposed on the porous Si surface; a first plate conformally disposed on the oxide layer; a first dielectric layer conformally disposed on the first plate; and a second plate conformally disposed on the first dielectric, where the first plate, the first dielectric layer, and the second plate, each have an irregular surface that generally conforms to the irregular surface of the porous Si surface.

Abstract: Radio frequency (RF) circuits generate noise that can interfere with other RF circuits on the same semiconductor die. An isolation material disposed in an isolation region between a first active region of a first RF circuit and a second active region of a second RF circuit comprises a porosified region of the semiconductor material of the semiconductor die. The isolation material (e.g., porosified material) has a higher resistivity and lower permittivity than the semiconductor material to reduce transmission of noise interference between the first RF circuit and the second RF circuit. The isolation material in the isolation region of the semiconductor material comprises a porosity in the range 20% to 50% higher than the porosity of the semiconductor material in the first and second active regions. The porosified region has a lower permittivity and a higher resistivity than the non-porosified region to protect against the transmission of noise interference.

Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

Abstract: Disclosed is an antenna on glass (AOG) device having an air cavity at least partially formed in a photosensitive glass substrate. An air cavity structure is at least partially encloses the air cavity and wherein the air cavity structure at least partially formed from the photosensitive glass substrate. An antenna is formed from portion of a top conductive layer disposed on a top surface of the air cavity structure and at least partially overlapping the air cavity. A metallization structure is provided having a bottom conductive layer disposed on a bottom surface of the air cavity structure, wherein the bottom conductive layer is electrically coupled to the top metal layer by a conductive pillar disposed through the photosensitive glass substrate. In addition, the AOG device may integrate one or more MIM capacitors and/or inductors that allow for RF filtering and impedance matching.

Abstract: Surface acoustic wave (SAW) filter packages employing an enhanced thermally conductive cavity frame for heat dissipation, and related fabrication methods are disclosed. The SAW filter package also includes a cavity frame comprising a perimeter structure and a cavity inside the perimeter structure coupled to a substrate of a piezoelectric material that contains interdigital transducers (IDTs). A cap substrate is disposed on the perimeter structure of the cavity frame to enclose an air cavity inside the perimeter structure between a substrate and the cap substrate. In exemplary aspects, to effectively dissipate heat generated in the SAW filter package to maintain the desired performance of the SAW filter, the cavity frame is comprised of a material that has an enhanced thermal conductivity. The heat generated in the SAW filter package can more effectively be dissipated, particularly at edges and corners of the cavity frame where hot spots can particularly occur.

Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

Abstract: A radio frequency integrated circuit (RFIC) includes a bulk semiconductor substrate. The RFIC also includes a compound semiconductor field effect transistor (FET). The compound semiconductor FET is composed of a gallium nitride (GaN) epitaxial stack in a trench in the bulk semiconductor substrate having sidewall spacers. The sidewall spacers are between the GaN epitaxial stack and sidewalls of the trench. A carbonized surface layer is at a base of the trench and coupled to the GaN epitaxial stack. The RFIC further includes a complementary metal oxide semiconductor (CMOS) transistor integrated with the compound semiconductor FET on the bulk semiconductor substrate.

Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

Abstract: A surface acoustic wave (SAW) device includes a first interdigital transducer (IDT) and a second IDT each including interdigital electrodes disposed on a first surface of a substrate of piezoelectric material. The SAW device includes a diamond bridge enclosing an air cavity over a wave propagation region on the first surface of the substrate. The diamond bridge has a reduced height and provides improved thermal conductivity to avoid a reduction in performance and/or life span caused by heat generated in the SAW device. A process of fabricating a SAW device includes forming the first IDT and the second IDT in a metal layer on a first surface of a substrate comprising a piezoelectric material, the first IDT and the second IDT disposed in a wave propagation region of the first surface of the substrate, and forming a diamond bridge disposed above the wave propagation region.

Abstract: Certain aspects provide an integrated circuit (IC) including a resonator. One example IC generally includes a substrate, a first oxide region disposed above the substrate, and a resonator. The resonator may include a piezoelectric layer, a second oxide region disposed below the piezoelectric layer and bonded to the first oxide region, and a cavity in the second oxide region, wherein at least a portion of the second oxide region is below the cavity.

Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

Abstract: Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.

Abstract: An integrated circuit (IC) package includes a chip. The chip has a front-side surface and a backside surface, opposite the front-side surface. The front-side surface of the chip includes a plurality of bump sites. The integrated circuit package also includes a plurality of dies. Each of the plurality of dies are composed of integrated passive devices. The plurality of dies have conformal die edge patterns to enable placement of a front-side surface of each of the plurality of dies on predetermined portions of the plurality of bumps sites on the front-side surface of the chip.

Abstract: A substrate that includes an encapsulation layer, a first acoustic resonator, a second acoustic resonator, at least one first dielectric layer, a plurality of first interconnects, at least one second dielectric layer, and a plurality of second interconnects. The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate comprising a first thickness. The second acoustic is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.