Patents by Inventor Je-Hsiung Lan

Je-Hsiung Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9343399
    Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Je-Hsiung Lan, Chengjie Zuo, Changhan Hobie Yun, Jonghae Kim, Daeik Daniel Kim, Mario Francisco Velez, Robert Paul Mikulka, Niranjan Sunil Mudakatte
  • Patent number: 9331665
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Patent number: 9203373
    Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Lan, Daeik D. Kim, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Patent number: 9090499
    Abstract: A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light.
    Type: Grant
    Filed: March 10, 2013
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: John H. Hong, Kenji Nomura, Je-Hsiung Lan
  • Patent number: 8988760
    Abstract: Encapsulation is provided to electromechanical devices to protect the devices from such environmental hazards as moisture and mechanical shock. In addition to the encapsulation layer providing protection from environmental hazards, the encapsulation layer is additionally planarized so as to function as a substrate for additional circuit elements formed above the encapsulation layer.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: March 24, 2015
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Je-Hsiung Lan
  • Publication number: 20150061813
    Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
    Type: Application
    Filed: January 14, 2014
    Publication date: March 5, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Xiangdong Zhang, Jonghae Kim, Je-Hsiung Lan
  • Publication number: 20150035162
    Abstract: An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chengjie Zuo, Mario Francisco Velez, Daeik D. Kim, David F. Berdy, Changhan Yun, Robert P. Mikulka, Jonghae Kim, Matthew M. Nowak
  • Publication number: 20150014812
    Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.
    Type: Application
    Filed: January 7, 2014
    Publication date: January 15, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Je-Hsiung LAN, Chengjie ZUO, Changhan Hobie YUN, Jonghae KIM, Daeik Daniel KIM, Mario Francisco VELEZ, Robert Paul MIKULKA, Niranjan Sunil MUDAKATTE
  • Patent number: 8922974
    Abstract: Tunable MEMS resonators having adjustable resonance frequency and capable of handling large signals are described. In one exemplary design, a tunable MEMS resonator includes (i) a first part having a cavity and a post and (ii) a second part mated to the first part and including a movable layer located under the post. Each part may be covered with a metal layer on the surface facing the other part. The movable plate may be mechanically moved by a DC voltage to vary the resonance frequency of the MEMS resonator. The cavity may have a rectangular or circular shape and may be empty or filled with a dielectric material. The post may be positioned in the middle of the cavity. The movable plate may be attached to the second part (i) via an anchor and operated as a cantilever or (ii) via two anchors and operated as a bridge.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Evgeni P Gousev, Wenyue Zhang, Manish Kothari, Sang-June Park
  • Publication number: 20140374914
    Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.
    Type: Application
    Filed: July 19, 2013
    Publication date: December 25, 2014
    Inventors: Daeik D. Kim, Je-Hsiung Lan, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim, Changhan Yun
  • Publication number: 20140354372
    Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.
    Type: Application
    Filed: September 6, 2013
    Publication date: December 4, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Daeik D. Kim, Mario Francisco Velez, Changhan Yun, Je-Hsiung Lan, Robert P. Mikulka, Matthew M. Nowak
  • Publication number: 20140354378
    Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.
    Type: Application
    Filed: October 16, 2013
    Publication date: December 4, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Chengjie ZUO, Jonghae KIM, Changhan Hobie YUN, Daeik Daniel KIM, Mario Francisco VELEZ, Je-Hsiung LAN, Robert Paul MIKULKA, Matthew Michael NOWAK
  • Publication number: 20140327508
    Abstract: An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: Qualcomm Incorporated
    Inventors: Daeik D. Kim, Kangho Lee, David F. Berdy, Mario Francisco Velez, Jonghae Kim, Je-Hsiung Lan, Changhan Yun, Niranjan Sunil Mudakatte, Robert P. Mikulka
  • Publication number: 20140327510
    Abstract: An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Daeik D. Kim, David F. Berdy, Chengjie Zuo, Mario Francisco Velez, Changhan Yun, Robert P. Mikulka, Jonghae Kim, Je-Hsiung Lan
  • Publication number: 20140327496
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Publication number: 20140266494
    Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Publication number: 20140268616
    Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Je-Hsiung Lan, Chengjie Zuo, Changhan Yun, David F. Berdy, Daeik D. Kim, Robert P. Mikulka, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20140251947
    Abstract: A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light.
    Type: Application
    Filed: March 10, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: John H. HONG, Kenji NOMURA, Je-Hsiung LAN
  • Publication number: 20140197902
    Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Lan, Daeik D. Kim, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Publication number: 20140138792
    Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chi Shun Lo, Je-Hsiung Lan, Mario Francisco Velez, Jonghae Kim