Patents by Inventor Je-Hsiung Lan

Je-Hsiung Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171112
    Abstract: An RF diplexer is provided that includes a first channel and a second channel. The first channel includes a first primary inductor. Similarly, the second channel includes a second primary inductor. A first directional coupler for the first channel includes a first transformer formed by the first primary inductor and also a first secondary inductor. A first terminal for the first secondary inductor is a coupled port for the first directional coupler. A second directional coupler for the second channel includes a second transformer formed by the second primary inductor and also a second secondary inductor. A first terminal for the second secondary inductor is a coupled port for the second directional coupler.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yunfei Ma, Chengjie Zuo, David Berdy, Daeik Kim, Changhan Yun, Je-Hsiung Lan, Mario Velez, Niranjan Sunil Mudakatte, Robert Mikulka, Jonghae Kim
  • Patent number: 10116285
    Abstract: A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 10038422
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Patent number: 10002700
    Abstract: In a particular embodiment, a device includes a low-loss substrate, a first inductor structure, and an air-gap. The first inductor structure is between the low-loss substrate and a second inductor structure. The first inductor structure is aligned with the second inductor structure to form a transformer. The air-gap is between the first inductor structure and the second inductor structure.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 19, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, John H. Hong
  • Patent number: 9935166
    Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 3, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chengjie Zuo, Changhan Yun, David F. Berdy, Daeik D. Kim, Robert P. Mikulka, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20180062617
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Publication number: 20170373175
    Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Shiqun GU, Gengming TAI, Je-Hsiung LAN, Matthew Michael NOWAK, Miguel MIRANDA CORBALAN, Steve FANELLI
  • Patent number: 9813043
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Publication number: 20170279469
    Abstract: An RF diplexer is provided with an integrated diplexer that shares a primary inductor included in a channel within the RF diplexer.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Yunfei Ma, Chengjie Zuo, David Berdy, Daeik Kim, Changhan Yun, Je-Hsiung Lan, Mario Velez, Niranjan Sunil Mudakatte, Robert Mikulka, Jonghae Kim
  • Publication number: 20170134007
    Abstract: A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 9634645
    Abstract: A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Lan, Chi Shun Lo, Jonghae Kim, Mario Francisco Velez, John H. Hong
  • Patent number: 9634640
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Publication number: 20170084523
    Abstract: Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Jie FU, Daeik Daniel KIM, Manuel ALDRETE, Chin-Kwan KIM, David BERDY, Niranjan Sunil MUDAKATTE, Changhan YUN, Je-Hsiung LAN, Jonghae KIM
  • Publication number: 20160358709
    Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Daeik Daniel Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Xiangdong Zhang, Jonghae Kim, Je-Hsiung Lan
  • Patent number: 9449753
    Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 20, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Daeik Daniel Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Xiangdong Zhang, Jonghae Kim, Je-Hsiung Lan
  • Patent number: 9431473
    Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chi Shun Lo, Je-Hsiung Lan, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9425761
    Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 23, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Chengjie Zuo, Jonghae Kim, Changhan Hobie Yun, Daeik Daniel Kim, Mario Francisco Velez, Je-Hsiung Lan, Robert Paul Mikulka, Matthew Michael Nowak
  • Patent number: 9401689
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 26, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Publication number: 20160204758
    Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Patent number: 9355967
    Abstract: An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik D. Kim, Je-Hsiung Lan, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim, Changhan Yun