Abstract: Disclosed is a gallium arsenide (GaAs) enabled tunable filter for, e.g., 6 GHz Wi-Fi RF Frontend, with integrated high-performance varactors, metal-insulator-metal (MIM) capacitors, and 3D solenoid inductors. The tunable filter comprises a hyper-abrupt variable capacitor (varactor) high capacitance tuning ratio. The tunable filter also comprises a GaAs substrate in which through-GaAs-vias (TGV) are formed. The varactor along with the MIM capacitors and the 3D inductors is formed in an upper conductive structure on upper surface of the GaAs substrate. Lower conductive structure comprising lower conductors is formed on lower surface of the GaAs substrate. Electrical coupling between the lower and upper conductive structures is provided by the TGVs. The tunable filter can be integrated with radio frequency front end (RFFE) devices.

Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

Abstract: Disclosed is an antenna on glass (AOG) device having an air cavity at least partially formed in a photosensitive glass substrate. An air cavity structure is at least partially encloses the air cavity and wherein the air cavity structure at least partially formed from the photosensitive glass substrate. An antenna is formed from portion of a top conductive layer disposed on a top surface of the air cavity structure and at least partially overlapping the air cavity. A metallization structure is provided having a bottom conductive layer disposed on a bottom surface of the air cavity structure, wherein the bottom conductive layer is electrically coupled to the top metal layer by a conductive pillar disposed through the photosensitive glass substrate. In addition, the AOG device may integrate one or more MIM capacitors and/or inductors that allow for RF filtering and impedance matching.

Abstract: A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.

Abstract: A semiconductor device having metamorphic high electron mobility transistor (HEMT)-heterojunction bipolar transistor (HBT) integration on a semiconductor substrate. An example semiconductor device generally includes a semiconductor substrate, a bipolar junction transistor (BJT) disposed above the semiconductor substrate and comprising indium, and a HEMT disposed above the semiconductor substrate and comprising indium.

Abstract: A package that includes a first filter comprising a first polymer, a substrate cap, a second filter comprising a second polymer frame, at least one interconnect, an encapsulation layer and a plurality of through encapsulation vias. The substrate cap is coupled to the first polymer frame such that a first void is formed between the substrate cap and the first filter. The second polymer frame is coupled to the substrate cap such that a second void is formed between the substrate cap and the second filter. The at least one interconnect is coupled to the first filter and the second filter. The encapsulation layer encapsulates the first filter, the substrate cap, the second filter, and the at least one interconnect. The plurality of through encapsulation vias coupled to the first filter.

Abstract: A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a powder distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.

Abstract: A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a power distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.

Abstract: A 3D integrated circuit (3D IC) chip is described. The 3D IC chip includes a die having a compound semiconductor high electron mobility transistor (HEMT) active device. The compound semiconductor HEMT active device is composed of compound semiconductor layers on a single crystal, compound semiconductor layer. The 3D IC chip also includes an acoustic device integrated in the single crystal, compound semiconductor layer. The 3D IC chip further includes a passive device integrated in back-end-of-line layers of the die on the single crystal, compound semiconductor layer.

Abstract: Certain aspects provide a three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. For example, certain aspects provide a semiconductor device that generally includes one or more first integrated circuits (ICs), a first plurality of pads coupled to components of the one or more first ICs, one or more second ICs, forming glass (FG) material disposed adjacent to the one or more second ICs, and a second plurality of pads, wherein at least one of the second plurality of pads is coupled to components of the one or more second ICs, and wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads.

Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

Abstract: Certain aspects provide an integrated circuit (IC) including a resonator. One example IC generally includes a substrate, a first oxide region disposed above the substrate, and a resonator. The resonator may include a piezoelectric layer, a second oxide region disposed below the piezoelectric layer and bonded to the first oxide region, and a cavity in the second oxide region, wherein at least a portion of the second oxide region is below the cavity.

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate with a carbonized layer. An example semiconductor device generally includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a diamond substrate, a carbonized layer disposed above the diamond substrate, and a first transistor disposed above the carbonized layer, the first transistor comprising gallium nitride. The second semiconductor die is disposed above the first semiconductor die, where the second semiconductor die includes a second transistor comprising a different semiconductor material than the first transistor.

Abstract: Certain aspects provide a three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. For example, certain aspects provide a semiconductor device that generally includes one or more first integrated circuits (ICs), a first plurality of pads coupled to components of the one or more first ICs, one or more second ICs, forming glass (FG) material disposed adjacent to the one or more second ICs, and a second plurality of pads, wherein at least one of the second plurality of pads is coupled to components of the one or more second ICs, and wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads.

Abstract: Active devices in an integrated circuit (IC) die package, such as in a radio frequency front end (RFFE) package can generate significant amount of heat. This problem can become acute especially as the operating frequency is high such as in 5G NR. Also, electromagnetic interference issues can arise in such packages. One or more techniques to mitigate thermal and electrical interference issues in IC die packages are presented.

Abstract: Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.

Abstract: Disclosed are devices and methods for semiconductor devices including a ceramic substrate. Aspects disclosed include semiconductor device including an electrical component, an alumina ceramic substrate and a substrate-film. The substrate-film is deposited on the alumina ceramic substrate. The substrate-film has a planar substrate-film surface opposite the alumina ceramic substrate. The electrical component is formed on the substrate-film surface of the substrate-film on the alumina ceramic substrate.

Abstract: 3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

Abstract: A semiconductor device having heterogeneous transistors integrated on a diamond substrate. An example semiconductor device generally includes a diamond substrate, a first transistor disposed above the diamond substrate, the first transistor comprising gallium nitride, and a second transistor disposed above the diamond substrate, the second transistor comprising a different semiconductor than the first transistor.

Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.