Abstract: A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

Abstract: A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

Abstract: A method for detecting the presence of on-body concealed objects includes receiving a visible-domain camera image for a scene, determining, using the visible-domain camera image, a region of interest where a subject is present, receiving an infrared-domain camera image and a millimeter-wave (mmwave) radar image that each cover the region of interest, determining emissivity information for the region of interest using the infrared-domain camera image, determining reflectivity information for the region of interest using the mmwave radar image and determining a concealed object classification for the subject based on the emissivity information and the reflectivity information. A corresponding system and computer program product for executing the above method are also disclosed herein.

Abstract: A phased array antenna includes an antenna array substrate having a plurality of antenna elements. At least two beamformers are coupled to the plurality of antenna elements. At least two filters support different frequency bands and are respectively coupled to the at least two beamformers. A frequency converter is coupled to the at least two filters, the frequency converter including one intermediate frequency (IF) port and at least two radio frequency (RF) ports. The one IF port of the frequency converter is configured to support the at least two beamformers via the at least two RF ports. A first beamformer of the at least two beamformers is coupled to a first filter of the at least two filters to form a first beam in a direction different than a second beamformer of the first two beamformers coupled to a second filter of the at least two filters.

Abstract: An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

Abstract: A phased array antenna includes an antenna array substrate having a plurality of antenna elements. At least two beamformers are coupled to the plurality of antenna elements. At least two filters support different frequency bands and are respectively coupled to the at least two beamformers. A frequency converter is coupled to the at least two filters, the frequency converter including one intermediate frequency (IF) port and at least two radio frequency (RF) ports. The one IF port of the frequency converter is configured to support the at least two beamformers via the at least two RF ports. A first beamformer of the at least two beamformers is coupled to a first filter of the at least two filters to form a first beam in a direction different than a second beamformer of the first two beamformers coupled to a second filter of the at least two filters.

Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

Abstract: An approach to creating a tamper-resistant field programmable gate array (FPGA) and remotely reprogramming the tamper-resistant FPGA. In one aspect, determining if an encryption key is stored in a physical unclonable function (PUF) of the FPGA. Further, responsive to the encryption key not being stored in a PUF, writing an encryption key in tamper resistant memory associated with a back end of the line (BEOL) of the FPGA. In another aspect, writing a program key and a look-up table (LUT) in the tamper resistant memory.

Abstract: A method for detecting the presence of on-body concealed objects includes receiving a visible-domain camera image for a scene, determining, using the visible-domain camera image, a region of interest where a subject is present, receiving an infrared-domain camera image and a millimeter-wave (mmwave) radar image that each cover the region of interest, determining emissivity information for the region of interest using the infrared-domain camera image, determining reflectivity information for the region of interest using the mmwave radar image and determining a concealed object classification for the subject based on the emissivity information and the reflectivity information. A corresponding system and computer program product for executing the above method are also disclosed herein.

Abstract: A method for detecting the presence of on-body concealed objects includes receiving a visible-domain camera image for a scene, determining, using the visible-domain camera image, a region of interest where a subject is present, receiving an infrared-domain camera image and a millimeter-wave (mmwave) radar image that each cover the region of interest, determining emissivity information for the region of interest using the infrared-domain camera image, determining reflectivity information for the region of interest using the mmwave radar image and determining a concealed object classification for the subject based on the emissivity information and the reflectivity information. A corresponding system and computer program product for executing the above method are also disclosed herein.

Abstract: A method for detecting the presence of on-body concealed objects includes receiving a visible-domain camera image for a scene, determining, using the visible-domain camera image, a region of interest where a subject is present, receiving an infrared-domain camera image and a millimeter-wave (mmwave) radar image that each cover the region of interest, determining emissivity information for the region of interest using the infrared-domain camera image, determining reflectivity information for the region of interest using the mmwave radar image and determining a concealed object classification for the subject based on the emissivity information and the reflectivity information. A corresponding system and computer program product for executing the above method are also disclosed herein.

Abstract: An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

Abstract: An imaging system is provided. A first imaging system captures initial sensor data in a form of visible domain data. A second imaging system captures subsequent sensor data in a form of second domain data, wherein the initial and subsequent sensor data are of different spectral domains. A controller subsystem detects at least one region of interest in real-time by applying a machine learning technique to the visible domain data, localizes at least one object of interest in the at least one region of interest to generate positional data for the at least one object of interest, and autonomously steers a point of focus of the second imaging system to a region of a scene including the object of interest to capture the second domain data responsive to the positional data.

Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

Abstract: Methods and systems for tag-based identification include receiving a set of parameters at a user device from a remote server. A counterfeit-proof identification tag is read using a sensor in the user device using the set of parameters. Features of the counterfeit-proof identification tag are extracted in accordance with a feature extraction function, using a processor, to generate a tag bit sequence. A challenge function is applied to the extracted features to generate a result. The result is transmitted to the remote server to authenticate the counterfeit-proof identification tag. The counterfeit-proof identification tag is authenticated with a tag database at the remote server.

Abstract: Systems, devices, and techniques facilitating wirelessly charging and/or communicating with one or more electronic devices (e.g., electronic wearable devices) are provided. A device can comprise a memory and a storage component that can be operatively coupled to the memory. The storage component can comprise one or more recesses that can receive a second device that can be charged by the storage component. The storage component can comprise a charging circuit and an inductive circuit that can be coupled to the charging circuit. The storage component can harvest energy from one or more energy sources to charge the charging circuit. Based on the energy harvested, the inductive circuit can inductively couple to the second device having a second inductive circuit and positioned in at least one of the recesses and the inductive circuit can charge a power source of the second device.

Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.

Abstract: Methods and systems for tag-based identification include receiving a set of parameters at a user device from a remote server. A counterfeit-proof identification tag is read using a sensor in the user device using the set of parameters. Features of the counterfeit-proof identification tag are extracted in accordance with a feature extraction function, using a processor, to generate a tag bit sequence. A challenge function is applied to the extracted features to generate a result. The result is transmitted to the remote server to authenticate the counterfeit-proof identification tag. The counterfeit-proof identification tag is authenticated with a tag database at the remote server.

Abstract: Methods and systems for tag-based identification include reading a counterfeit-proof identification tag using a sensor in a user device. Features of the identification tag are extracted in accordance with a feature extraction function, using a processor, to generate a tag bit sequence. A challenge function is applied to the extracted features to generate a result. The result is transmitted to a remote server to authenticate the identification tag.

Abstract: Antenna devices, antenna systems and methods of their fabrication are disclosed. One such antenna device includes a semiconductor chip and a chip package. The semiconductor chip includes at least one antenna that is integrated into a dielectric layer of the semiconductor chip and is configured to transmit electromagnetic waves. In addition, the chip package includes at least one ground plane, where the semiconductor chip is mounted on the chip package such that the ground plane(s) is disposed at a predetermined distance from the antenna to implement a reflection of at least a portion of the electromagnetic waves.