Abstract: Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

Abstract: Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.

Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

Abstract: Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.

Abstract: Embodiments include package structures having integrated waveguides to enable high data rate communication between package components. For example, a package structure includes a package substrate having an integrated waveguide, and first and second integrated circuit chips mounted to the package substrate. The first integrated circuit chip is coupled to the integrated waveguide using a first transmission line to waveguide transition, and the second integrated circuit chip is coupled to the integrated waveguide using a second transmission line to waveguide transition. The first and second integrated circuit chips are configured to communicate by transmitting signals using the integrated waveguide within the package carrier.

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT, an NPN BJT or a pair of complementary PNP BJT and NPN BJT, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench.

Abstract: A semiconductor structure is provided in which a plurality of waveguide structures are embedded within a semiconductor handle substrate. Each waveguide structure includes, from bottom to top, a bottom oxide portion, a waveguide core material portion and a top oxide portion. An oxide capping layer is present on topmost surfaces of each waveguide structure and a topmost surface of the semiconductor handle substrate. A plurality of semiconductor devices is located above a topmost surface of the oxide capping layer. The structure has thicker buried oxide regions defined by the combined thicknesses of the top oxide portion and the oxide capping layer located in some areas, while thinner buried oxide regions defined only by the thickness of the oxide capping layer are present in other areas of the structure.

Abstract: A semiconductor structure is provided in which a plurality of waveguide structures are embedded within a semiconductor handle substrate. Each waveguide structure includes, from bottom to top, a bottom oxide portion, a waveguide core material portion and a top oxide portion. An oxide capping layer is present on topmost surfaces of each waveguide structure and a topmost surface of the semiconductor handle substrate. A plurality of semiconductor devices is located above a topmost surface of the oxide capping layer. The structure has thicker buried oxide regions defined by the combined thicknesses of the top oxide portion and the oxide capping layer located in some areas, while thinner buried oxide regions defined only by the thickness of the oxide capping layer are present in other areas of the structure.

Abstract: A method of forming monolithically integrated III-V optoelectronics with a silicon complementary metal-oxide-semiconductor (CMOS) device. The method may include; forming a buried waveguide in a buried oxide (BOX) layer of a semiconductor-on-insulator (SOI) substrate; forming a first optoelectronic device and a second optoelectronic device adjacent to the buried waveguide; and forming a CMOS device on a semiconductor layer above the BOX layer.

Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities.

Abstract: Methods, systems and devices related to authentication of chips using physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.

Abstract: A semiconductor structure is provided in which a plurality of waveguide structures are embedded within a semiconductor handle substrate. Each waveguide structure includes, from bottom to top, a bottom oxide portion, a waveguide core material portion and a top oxide portion. An oxide capping layer is present on topmost surfaces of each waveguide structure and a topmost surface of the semiconductor handle substrate. A plurality of semiconductor devices is located above a topmost surface of the oxide capping layer. The structure has thicker buried oxide regions defined by the combined thicknesses of the top oxide portion and the oxide capping layer located in some areas, while thinner buried oxide regions defined only by the thickness of the oxide capping layer are present in other areas of the structure.

Abstract: A semiconductor structure is provided in which a plurality of waveguide structures are embedded within a semiconductor handle substrate. Each waveguide structure includes, from bottom to top, a bottom oxide portion, a waveguide core material portion and a top oxide portion. An oxide capping layer is present on topmost surfaces of each waveguide structure and a topmost surface of the semiconductor handle substrate. A plurality of semiconductor devices is located above a topmost surface of the oxide capping layer. The structure has thicker buried oxide regions defined by the combined thicknesses of the top oxide portion and the oxide capping layer located in some areas, while thinner buried oxide regions defined only by the thickness of the oxide capping layer are present in other areas of the structure.

Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.

Abstract: An optical interconnect is located on a surface of a semiconductor handle substrate. The optical interconnect includes a waveguide core material portion that is completely surrounded on all four sides by a dielectric oxide-containing cladding structure. The dielectric oxide-containing material of the dielectric oxide-containing cladding structure that is located laterally adjacent end segments of the waveguide core material portion is configured to include a sidewall surface that can receive and transmit light. A plurality of semiconductor devices can be formed above the topmost dielectric oxide-containing material of the dielectric oxide-containing cladding structure.

Abstract: Package structures are provided for integrally packaging antennas with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems that operate in the millimeter-wave and terahertz frequency ranges. For example, a package structure includes an RFIC chip, and an antenna package bonded to the RFIC chip. The antenna package includes a glass substrate, at least one planar antenna element formed on a first surface of the glass substrate, a ground plane formed on a second surface of the glass substrate, opposite the first surface, and an antenna feed line formed through the glass substrate and connected to the at least one planar antenna element. The antenna package is bonded to a surface of the RFIC chip using a layer of adhesive material.

Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.