Abstract: A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

Abstract: Manufacturable processes and the resultant structures utilize metal hydride as an internal source of hydrogen to enhance heat removal within semiconductor packages that employ low dielectric constant materials. The use of a metal hydride heated by internal or external sources facilitates pressurizing hydrogen gas or hydrogen-helium gas mixtures within a hermetically-sealed package. The configuration of the metal hydride can include, where needed to generate the pressure required in larger packages, a relatively large area of metal hydride material on at least one or a plurality of hydrogen generation-dedicated chips. Alternatively, the configuration can include at least one or a plurality of relatively small “islands” of metal hydride material on each of at least one or a plurality of integrated circuit-bearing chips.

Abstract: An electronic package comprised of multiple chip stacks attached together to form a single, compact electronic module. The module is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A structure that allows for densely-packed, multiple chip stack electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic packages.

Abstract: A typical integrated circuit includes millions of microscopic transistors, resistors, and other components interconnected to define a circuit, for example a memory circuit. Occasionally, one or more of the components are defective and fabricators selectively replace them by activating spare, or redundant, components included within the circuit. One way of activating a redundant component is to rupture an antifuse that effectively connects the redundant component into the circuit. Unfortunately, conventional antifuses have high and/or unstable electrical resistances which compromise circuit performance and discourage their use. Accordingly, the inventors devised an exemplary antifuse structure that includes three normally disconnected conductive elements and a programming mechanism for selectively moving one of the elements to electrically connect the other two.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is position proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed that allows for densely-packed, multi-chip electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic package.

Abstract: A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The floating gate has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate and is separated from the floating gate by a compositionally graded mixed metal oxide tunnel barrier intergate insulator.

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.

Abstract: A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed that allows for densely-packed, multi-chip electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic package.

Abstract: Flash memory cells are provided that include a first source/drain region and a second source/drain region separated by a channel region. A first gate opposes. A first gate insulator separates the first gate from the channel. The first gate insulator includes a graded composition gate insulator. A second gate is separated from the first gate insulator by a second gate insulator. The above memory cells produce gate insulators with less charging at the interface between composite insulator layers and provide gate insulators with low surface state densities. The memory cells substantially reduce large barrier heights or energy problems by using dielectrics having suitably, adjustably lower barrier heights in contact with the polysilicon floating gate. Such adjustable barrier heights of controlled thicknesses can be formed using a silicon suboxide and a silicon oxycarbide dielectrics prepared according to the process as described herein.

Abstract: A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

Abstract: A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

Abstract: An electronic package comprised of multiple chip stacks attached together to form a single, compact electronic module. The module is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A structure that allows for densely-packed, multiple chip stack electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic packages.