Patents by Inventor Jin-Aun Ng
Jin-Aun Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854905Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
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Patent number: 11749679Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: GrantFiled: July 2, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
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Patent number: 11670711Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.Type: GrantFiled: November 30, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 11545490Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.Type: GrantFiled: June 8, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Aun Ng, Yu-Chao Lin, Tung-Ying Lee
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Publication number: 20220359506Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun NG, Yu-Chao LIN, Tung-Ying LEE
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Publication number: 20220359309Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
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Publication number: 20220336454Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and multiple nanostructures over the substrate. The semiconductor device structure also includes a semiconductor fin between the substrate and the nanostructures. The semiconductor device structure further includes a gate stack wrapped around the nanostructures. The gate stack includes a gate dielectric layer, and the gate dielectric layer continuously extends along a bottommost nanostructure of the nanostructures and an upper portion of the semiconductor fin.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun NG, Kuo-Cheng CHIANG, Hung-Li CHIANG, Tzu-Chiang CHEN, I-Sheng CHEN
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Patent number: 11404325Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.Type: GrantFiled: May 8, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
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Patent number: 11398476Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.Type: GrantFiled: December 27, 2019Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen
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Publication number: 20210335785Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
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Patent number: 11133221Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a plurality of first nanostructures, a plurality of second nanostructures, two tensile epitaxial structures, two compressive epitaxial structures, and a dielectric layer over the substrate. The method includes forming a gate dielectric layer over the first nanostructures and the second nanostructures. The method includes forming a first work function metal layer over the gate dielectric layer over the first nanostructures. The method includes forming a second work function metal layer over the gate dielectric layer over the second nanostructures. The method includes forming a compressive gate electrode layer over the first work function metal layer using an atomic layer deposition process or a chemical vapor deposition process. The method includes forming a tensile gate electrode layer over the second work function metal layer using a physical vapor deposition process.Type: GrantFiled: June 17, 2020Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun Ng, Sai-Hooi Yeong
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Patent number: 11094545Abstract: A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.Type: GrantFiled: July 16, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
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Patent number: 11075199Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.Type: GrantFiled: February 11, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
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Publication number: 20210183855Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure.Type: ApplicationFiled: June 8, 2020Publication date: June 17, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun NG, Yu-Chao LIN, Tung-Ying LEE
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Publication number: 20210183707Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a plurality of first nanostructures, a plurality of second nanostructures, two tensile epitaxial structures, two compressive epitaxial structures, and a dielectric layer over the substrate. The method includes forming a gate dielectric layer over the first nanostructures and the second nanostructures. The method includes forming a first work function metal layer over the gate dielectric layer over the first nanostructures. The method includes forming a second work function metal layer over the gate dielectric layer over the second nanostructures. The method includes forming a compressive gate electrode layer over the first work function metal layer using an atomic layer deposition process or a chemical vapor deposition process. The method includes forming a tensile gate electrode layer over the second work function metal layer using a physical vapor deposition process.Type: ApplicationFiled: June 17, 2020Publication date: June 17, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jin-Aun NG, Sai-Hooi YEONG
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Patent number: 11004747Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: GrantFiled: May 11, 2020Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Publication number: 20210083087Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
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Patent number: 10854742Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.Type: GrantFiled: June 24, 2019Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20200273754Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
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Publication number: 20200273757Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge