Patents by Inventor Jin-Aun Ng
Jin-Aun Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9252224Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: August 28, 2014Date of Patent: February 2, 2016Assignee: Taiwan semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Harry-Hak-Lay Chuang
-
Patent number: 9219125Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: GrantFiled: April 11, 2014Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
-
Publication number: 20150214115Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Inventors: Wei Cheng Wu, Bao-Ru Young, Harry-Hak-lay Chuang, Jin-Aun Ng, Po-Nien Chen
-
Patent number: 9093559Abstract: A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.Type: GrantFiled: March 9, 2012Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Po-Nien Chen, Sheng-Chen Chung, Bao-Ru Young, Hak-Lay Chuang
-
Patent number: 9000533Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: GrantFiled: April 26, 2012Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Cheng Wu, Po-Nien Chen, Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang
-
Publication number: 20150004779Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Ming Zhu, Jin-Aun Ng, Chi-Wen Liu
-
Publication number: 20140367802Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: August 28, 2014Publication date: December 18, 2014Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, JUNG-HUI KAO, Yuan-Tien Tu, HUAN-JUST LIN, Chih-Tang Peng, Pei-Ren Jeng, BAO-RU YOUNG, HARRY-HAK-LA Y CHUANG
-
Patent number: 8871625Abstract: A method of fabricating a spacer structure which includes forming a dummy gate structure comprising a top surface and sidewall surfaces over a substrate and forming a spacer structure over the sidewall surfaces. Forming the spacer structure includes depositing a first oxygen-sealing layer on the dummy gate structure and removing a portion of the first oxygen-sealing layer on the top surface of the dummy gate structure, whereby the first oxygen-sealing layer remains on the sidewall surfaces. Forming the spacer structure further includes depositing an oxygen-containing layer on the first oxygen-sealing layer and the top surface of the dummy gate structure. Forming the spacer structure further includes depositing a second oxygen-sealing layer on the oxygen-containing layer and removing a portion of the second oxygen-sealing layer over the top surface of the dummy gate structure. Forming the spacer structure further includes thinning the second oxygen-sealing layer.Type: GrantFiled: May 2, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Ryan Chia-Jen Chen
-
Patent number: 8822283Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.Type: GrantFiled: September 24, 2011Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
-
Publication number: 20140203373Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: ApplicationFiled: April 11, 2014Publication date: July 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
-
Patent number: 8698252Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: GrantFiled: April 26, 2012Date of Patent: April 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Hak-Lay Chuang
-
Publication number: 20130320410Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
-
Patent number: 8586436Abstract: Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.Type: GrantFiled: March 20, 2012Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Ming Zhu, Chi-Wen Liu
-
Publication number: 20130285150Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Hak-Lay Chuang
-
Publication number: 20130285151Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Cheng Wu, Po-Nien Chen, Jin-Aun Ng, Bao-Ru Young, Harry Hak-Lay Chuang
-
Publication number: 20130270647Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.Type: ApplicationFiled: April 17, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Jin-Aun Ng, Chi-Wen Liu
-
Publication number: 20130249010Abstract: Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Jin-Aun Ng, Ming Zhu, Chi-Wen Liu
-
Publication number: 20130234254Abstract: A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Po-Nien Chen, Sheng-Chen Chung, Bao-Ru Young, Hak-Lay Chuang
-
Patent number: 8450161Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: May 7, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
-
Patent number: 8450834Abstract: This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.Type: GrantFiled: February 16, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Ryan Chia-Jen Chen