Patents by Inventor Jin-Aun Ng
Jin-Aun Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130056837Abstract: A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.Type: ApplicationFiled: September 24, 2011Publication date: March 7, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo, Chih-Yang Yeh, Hui-Wen Lin, Jung-Hui Kao, Yuan-Tien Tu, Huan-Just Lin, Chih-Tang Peng, Pei-Ren Jeng, Bao-Ru Young, Hak-Lay Chuang
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Patent number: 8373199Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: GrantFiled: July 29, 2011Date of Patent: February 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Wen-Chin Yang, Chien-Liang Chen, Chung-Hua Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Patent number: 8343867Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.Type: GrantFiled: September 16, 2011Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
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Patent number: 8329521Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.Type: GrantFiled: July 2, 2010Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Sheng-Chen Chung, Kai-Shyang You, Jin-Aun Ng, Wei Cheng Wu, Ming Zhu
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Publication number: 20120225529Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: May 7, 2012Publication date: September 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8193586Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: February 20, 2009Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
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Publication number: 20120009754Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.Type: ApplicationFiled: September 16, 2011Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun NG, Yu-Ying HSU, Chi-Ju LEE, Sin-Hua WU, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
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Publication number: 20120001259Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Hak-Lay Chuang, Bao-Ru Young, Sheng-Chen Chung, Kai-Shyang You, Jin-Aun Ng, Wei Cheng Wu, Ming Zhu
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Publication number: 20110278646Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: ApplicationFiled: July 29, 2011Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Wen-Chin Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Patent number: 8039388Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.Type: GrantFiled: March 24, 2010Date of Patent: October 18, 2011Assignee: Taiwam Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
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Publication number: 20110237040Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.Type: ApplicationFiled: March 24, 2010Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun NG, Yu-Ying HSU, Chi-Ju LEE, Sin-Hua WU, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
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Patent number: 8003467Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: GrantFiled: April 30, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Publication number: 20110198675Abstract: This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.Type: ApplicationFiled: February 16, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun NG, Bao-Ru Young, Harry-Hak-Lay Chuang, Ryan Chia-Jen Chen
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Publication number: 20100109088Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: ApplicationFiled: April 30, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Publication number: 20100044803Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: February 20, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang