Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.

Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Abstract: A semiconductor device with multiple zero differential transconductance includes: a conductive substrate; a first insulating layer and a second insulating layer disposed on the conductive substrate; a first semiconductor and a second semiconductor disposed on first portions of the first insulating layer and the second insulating layer, respectively; a first buffer layer and a second buffer layer disposed on electrode contact areas of the first semiconductor and the second semiconductor, respectively; and an anode electrode and a cathode electrode disposed on second portions, which are different from the first portions, of the first insulating layer and the second insulating layer and on the first buffer layer and the second buffer layer, respectively, wherein the first semiconductor and the second semiconductor are disposed in parallel with each other and connected by the anode electrode and the cathode electrode.

Abstract: Disclosed is a photodetector in which a plurality of conductive stripes spaced apart from each other are bonded onto a two-dimensional semiconductor thin-film, and a pitch between adjacent conductive stripes is controlled to selectively adjust a plasmonic resonance wavelength zone, such that the photodetector has a high absorbance and a wide detection zone at the same time. Further, a manufacturing method thereof is disclosed. The photodetector includes a semiconductor thin-film; and a plurality of conductive stripes bonded onto the semiconductor thin-film and extending in a parallel manner to each other and spaced apart from each other.

Abstract: A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip.

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

Abstract: Organic coating compositions, particularly antireflective coating compositions for use with an overcoated photoresist, are provided that comprise that a blend of two or more resins, where one resin has epoxy groups either pendant or fused to the polymer backbone. Preferred coating compositions include: 1) a first resin that comprises one or more epoxy reactive groups; and 2) a crosslinker resin that is distinct from the first resin and comprises epoxy groups.

Abstract: Tandem solar cell configurations are provided where at least one of the cells is a metal chalcogenide cell. A four-terminal tandem solar cell configuration has two electrically independent solar cells stacked on each other. A two-terminal solar cell configuration has two electrically coupled solar cells (same current through both cells) stacked on each other. Carrier selective contacts can be used to make contact to the metal chalcogenide cell (s) to alleviate the troublesome Fermi level pinning issue. Carrier-selective contacts can also remove the need to provide doping of the metal chalcogenide. Doping of the metal chalcogenide can be provided by charge transfer. These two ideas can be practiced independently or together in any combination.

Abstract: A polymer comprising a first repeating unit including an amino group protected by an alkoxycarbonyl group; a second repeating unit including a nucleophilic group; and a third repeating unit including a crosslinkable group, wherein the first repeating unit, the second repeating unit, and the third repeating unit are different from each other.

Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: A coating composition comprising a crosslinkable polyester polymer comprising an isocyanurate group and a crosslinkable group; a crosslinker; and an acid catalyst, wherein at least one of the crosslinkable polyester polymer and the crosslinker comprises an iodine-containing polymer.

Abstract: Disclosed is a photodetector in which a plurality of conductive stripes spaced apart from each other are bonded onto a two-dimensional semiconductor thin-film, and a pitch between adjacent conductive stripes is controlled to selectively adjust a plasmonic resonance wavelength zone, such that the photodetector has a high absorbance and a wide detection zone at the same time. Further, a manufacturing method thereof is disclosed. The photodetector includes a semiconductor thin-film; and a plurality of conductive stripes bonded onto the semiconductor thin-film and extending in a parallel manner to each other and spaced apart from each other.

Abstract: A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip.

Abstract: What is discussed is an interconnection member including (a) a main cable made of a flexible flat cable (FFC) including copper wires, (b) terminal parts branched from the main cable and electrically connected to at least one of the copper wires of the main cable, (c) a connecting part formed on one-side end of the main cable, and electrically and mechanically connected to a PCB and (d) at least one temperature sensing part branched from the main cable, wherein the at least one temperature sensing part comprises a first extending part extending from the main cable while sharing at least one copper wire of the copper wires of the main cable and a ceramic thermistor disposed on an end of the first extending part while being electrically connected to the first extending part.

Abstract: Provided is an interconnection member including: (a) a main cable made of a flexible flat cable (FFC) including a plurality of copper wires; (b) a plurality of terminal parts branched from the main cable and electrically connected to at least one of the copper wires of the main cable, the plurality of terminal parts being connected to the bus bars to sense voltages of the battery cells; (c) a connecting part formed on one-side end of the main cable, and electrically and mechanically connected to the PCB; and (d) at least one temperature sensing part branched from the main cable, adjacent to the connecting part, while sharing at least one of the copper wires of the main cable.

Abstract: A semiconductor device according to an embodiment may include a board, an insulation layer disposed on the board, a threshold voltage control layer disposed on the insulation layer, a first semiconductor layer disposed on the threshold voltage control layer, and a second semiconductor layer disposed on the threshold voltage control layer to cover a portion of the first semiconductor layer. A negative differential resistance device according to an embodiment has an advantageous effect in that the gate voltage enables a peak voltage to be freely controlled within an operation range of the device by forming the threshold voltage control layer.

Abstract: Provided is a semiconductor device with negative differential transconductance. The semiconductor device includes a substrate, a gate electrode formed on the substrate, an insulating layer formed on the gate electrode, a source electrode material layer formed on the insulating layer, a semiconductor material layer formed on the insulating layer to be hetero-joined to the source electrode material layer, a source electrode formed on the source electrode material layer, and a drain electrode formed on the semiconductor material layer. A work function of the source electrode material layer is controlled by a gate voltage applied through the gate electrode, and the source electrode material layer shows negative differential transconductance depending on a level of the gate voltage.

Abstract: Provided is a negative differential resistance element having a 3-dimension vertical structure. The negative differential resistance element having a 3-dimension vertical structure includes: a substrate; a first electrode that is formed on the substrate to receive a current; a second semiconductor material that is formed in some region of the substrate; a first semiconductor material that is deposited in some other region and the first electrode of the substrate and some region of an upper end of the second semiconductor material; an insulator that has a part vertically erected from the substrate, the other part vertically erected from the second semiconductor material, and an upper portion stacked with a first semiconductor material; and a second electrode that is formed at an upper end of the second semiconductor material to output a current, thereby significantly reducing an area of the device and greatly improving device scaling and integration.