Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output.

Abstract: An offset correction is automatically determined and routinely updated to reduce or eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. An offset control loop is provided for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value. The integration may be performed over at least one period of the sinusoidal wobble signal, and the correction added to the wobble signal.

Abstract: A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Abstract: A signal corresponding to data read from an optical storage medium is equalized to generate an equalized signal. A signal level of the equalized signal is determined, and an expected signal level of the equalized signal without high frequency distortion is determined. A comparison between the signal level of the equalized signal and the expected signal level is performed, and an amplitude of the equalized signal is adjusted based on the comparison of the actual signal level of the equalized signal and the expected signal level. The equalized signal is decoded after adjusting the amplitude of the equalized signal.

Abstract: A circuit including a wobble signal phase imperfection detector configured to detect and correct a phase transition imperfection in a first scaled wobble signal sample. The wobble signal phase imperfection detector includes an integrator configured to integrate the first scaled wobble signal sample over substantially a half-period portion of the wobble clock signal, and a selector configured to select as an output either i) the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal or ii) the first scaled wobble signal sample integrated over substantially the half-period portion of the wobble clock signal, wherein selection of the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal indicates that the phase transition imperfection does not exist with the first scaled wobble signal sample.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: Aspects of the disclosure provide a method for detecting land pre-pits. The method includes extracting a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium based on a land pre-pit threshold, detecting a bit stream pattern from the land pre-pit data stream, comparing one or more bits in the land pre-pit data stream at locations relative to the bit stream pattern with pre-known bit information, and adjusting the land pre-pit threshold based on the comparison.

Abstract: Devices, systems, methods, and other embodiments associated with clocking a radio frequency channel are described. In one embodiment, an apparatus includes a wobble channel logic configured to at least partially decode a digital wobble signal and configured to control a time base generator to generate a clock signal that is synchronized to wobble data. The apparatus further includes scaling logic to scale the clock signal to produce a scaled clock signal, and radio frequency channel logic configured to at least partially decode a digital radio frequency signal. The radio frequency channel logic is configured to be clocked by the clock signal and the wobble channel logic is configured to be clocked by the scaled clock signal.

Abstract: A system with a nonlinear element processes a replay signal with a scaling factor into a signal compensated for asymmetry. The replay signal may include data from an optical disk. The scaling factor may be estimated based on the compensated signal and a scaling factor gain. The replay signal and the compensated signal may be converted into digital signals and processed digitally. In one embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by a square of an amplitude of the replay signal added to the amplitude of the replay signal. In another embodiment, the compensated signal may be calculated as approximately the scaling factor multiplied by an absolute value of an amplitude of the replay signal added to the amplitude of the replay signal. A related method is also disclosed. Other embodiments are provided, and each of the embodiments described herein can be used alone or in combination with one another.

Abstract: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.

Abstract: Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

Abstract: In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

Abstract: Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.

Abstract: Aspects of the disclosure provide a method for efficiently calibrating an optical recording device. The method can include receiving a first signal corresponding to a wobbled track of a memory medium, phase-locking a second signal to the first signal, the second signal being used to extract embedded information in the wobbled track, and determining an optimum setting of the optical recording device based on a locking quality of the first signal and the second signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: An offset correction is automatically determined and routinely updated to reduce or eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. An offset control loop is provided for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value. The integration may be performed over at least one period of the sinusoidal wobble signal, and the correction added to the wobble signal.

Abstract: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output.