Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock.

Abstract: Aspects of the disclosure provide a method for detecting land pre-pits. The method includes detecting, based on a land pre-pit threshold, a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium, comparing a characteristic of the detected land pre-pit data stream in a specific number of wobble periods with a pre-determined land pre-pit characteristic in the specific number of wobble periods, and adjusting the land pre-pit threshold based on the comparison.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

Abstract: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

Abstract: Aspects of the disclosure provide a method for detecting land pre-pits. The method includes extracting a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium based on a land pre-pit threshold, detecting a bit stream pattern from the land pre-pit data stream, comparing one or more bits in the land pre-pit data stream at locations relative to the bit stream pattern with pre-known bit information, and adjusting the land pre-pit threshold based on the comparison.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

Abstract: Devices, systems, methods, and other embodiments associated with clocking a radio frequency channel are described. In one embodiment, an apparatus includes a wobble channel logic configured to at least partially decode a digital wobble signal and configured to control a time base generator to generate a clock signal that is synchronized to wobble data. The apparatus further includes downsampling logic to scale the clock signal to produce a scaled clock signal, and a radio frequency channel logic to at least partially decode a digital radio frequency signal. The clocking signal is connected to clock the radio frequency channel logic, and the scaled clocking signal is connected to clock the wobble channel logic.

Abstract: A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples.

Abstract: Aspects of the disclosure provide a method for detecting land pre-pits. The method can adaptively adjust a threshold for detecting the land pre-pits in order to improve the correctness of detecting. The method for detecting land pre-pits can include extracting a land pre-pit data stream from a reading signal based on a land pre-pit threshold, the reading signal corresponding to land pre-pits of an optical medium, comparing the land pre-pit data stream with format information of the optical medium to obtain an error signal, and adjusting the land pre-pit threshold based on the error signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

Abstract: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

Abstract: Aspects of the disclosure provide a method for efficiently calibrating an optical recording device. The method can include receiving a first signal corresponding to a wobbled track of a memory medium, phase-locking a second signal to the first signal, the second signal being used to extract embedded information in the wobbled track, and determining an optimum setting of the optical recording device based on a locking quality of the first signal and the second signal.

Abstract: An automated capability is provided in which an offset correction is automatically determined and routinely updated in order to reduce or otherwise eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. The capability is implemented through an improved offset control loop for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

Abstract: A method and apparatus for recovering clock timing from a bi-phase modulated portion of a high frequency modulation (HFM) signal. The HFM signal includes signal transitions between a high level and a low level. A clock count is initiated upon detection of a first signal transition in the bi-phase modulated portion of the HFM signal. The clock count corresponds to an expected clock timing of the HFM signal. The clock count is stopped upon detection of a second signal transition in the bi-phase modulated portion of the HFM signal subsequent to the first signal transition. An actual clock count includes a number of clock cycles occurring between the first and second signal transitions based on the expected clock timing. An expected clock count between signal transitions of the bi-phase modulated portion of the HFM signal is identified if the actual clock count between the first and second signal transitions falls within a range of clock counts.

Abstract: A method and apparatus for recovering clock timing from a hi-phase modulated portion of an HFM signal. The signal includes transitions between high and low levels. A clock count is initiated upon detection of a first transition, which corresponds to an expected clock timing of the signal. The count is stopped upon detection of a second transition. An actual clock count includes a number of clock cycles occurring between the transitions based on the expected timing. A first expected clock count between transitions is identified if the actual clock count between the transitions falls within a first range of clock counts. A first error between the actual and first expected clock counts is determined. A second expected clock count between transitions is identified if the actual clock count between transitions falls within a second range of clock counts. A second error between the actual expected clock counts is determined.