Abstract: In a circuit, a wobble detector detects a wobble signal from an optical recording medium and a synchronization signal based on the wobble signal and provides a wobble clock signal. A wobble signal phase imperfection detector responds to the wobble signal and detects and corrects a phase transition imperfection in the wobble signal. The imperfection detector integrates a first scaled wobble signal sample over a half period portion of the wobble clock signal; compares the first scaled wobble signal sample integrated over one period of the wobble clock signal to a variable threshold value; and based on the comparison, outputs either the half period integrated and scaled wobble sample or the first scaled wobble sample integrated over one period of the wobble clock signal. The imperfection detector further decodes the output to obtain wobble address period data.

Abstract: Devices, systems, methods, and other embodiments associated with wobble channel clocking are described. In one embodiment, an apparatus implemented with a clock generator, a clock scaling logic, radio frequency channel logic, and wobble channel log. The clock generator generates a clocking signal. The clock scaling logic scales the clocking signal to produce a scaled clocking signal. The radio frequency channel logic at least partially decodes a digital radio frequency signal from an optical disk. The wobble channel logic at least partially decodes a digital wobble signal from the optical disk. Either the clocking signal or the scaled clocking signal is used to clock the radio frequency channel logic, and the other clocking signal or the scaled clocking signal is used to clock the wobble channel.

Abstract: In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.

Abstract: A media defect compensation system and method may decouple effects of asymmetry from baseline error compensation computations. In some embodiments, a switching mechanism passes a baseline error signal into a baseline loop when a determination is made that a baseline error signal is not affected by asymmetry, and otherwise freezes the baseline loop when asymmetry may influence baseline error calculations.

Abstract: A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.

Abstract: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds.

Abstract: A specialized structure measures clock-to-data jitter in an optical memory interface by averaging the result of two second-order estimates of zero crossing using measured signal values on either side of the zero crossing. In one embodiment, a first estimate uses two sample points before the zero crossing and one sample point after while the second estimate uses one sample point before the zero crossing and sample two points after. An existing clock associated with an internal analog-to-digital converter is used to evenly space the samples in time. To simplify the second-order estimate calculations, the three samples of the exemplary embodiment are give x values of ?1, 0, and +1 respectively. Which of the two roots of the second-order estimates is used is based on the slope of the signal at the zero crossing.

Abstract: In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output.

Abstract: In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

Abstract: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

Abstract: One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e.g., where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.

Abstract: Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock.

Abstract: Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

Abstract: An automated capability is provided in which an offset correction is automatically determined and routinely updated in order to reduce or otherwise eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. The capability is implemented through an improved offset control loop for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value.

Abstract: Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

Abstract: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds.

Abstract: An apparatus and method are disclosed for decoding servo data recorded on a magnetic disk drive and detecting pinned layer reversals and signal errors, for example, errors due to noise. The servo data is encoded using wide-bi-phase encoding. This encoding is detected by a magneto-resistive sensor that senses the magnetization in domains passing by the sensor. The decoder includes an A/D converter for sampling the signals emitted by the sensor, to provide a sequence of the encoded data. A trellis, such as a Viterbi trellis, is employed to decode the samples generated by the converter. The trellis includes nodes representing states, connected by paths representing transitions, among the nodes. A quality value is generated for the transitions, the quality value representing the distance between each sample in the sequence output by the A/D converter and a corresponding expected sample.