Patents by Inventor John I. Garney

John I. Garney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7152125
    Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventors: John I. Garney, Robert J. Royer, Jr.
  • Patent number: 7130962
    Abstract: Processor-based systems which may include non-volatile write-back cache and a disk drive may flush cache when the processor-based system is shut down. Flushing large cache to a disk drive may consume large amounts of time. Sequentially writing dirty cache lines during a system shutdown may alleviate the need to flush dirty cache lines and may require much less time.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventor: John I. Garney
  • Patent number: 7085878
    Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: August 1, 2006
    Assignee: Intel Corporation
    Inventors: Robert J. Royer, Jr., John I. Garney
  • Patent number: 7007110
    Abstract: A method and apparatus for traversing a schedule with a bus master, the schedule having a plurality of elements, each element having information pertaining to one of a plurality of endpoints; executing transactions on a bus in accordance with the information pertaining to the plurality of endpoints; counting flow control events issued by individual endpoints; and skipping elements in the traversal of the schedule, the elements being skipped corresponding to endpoints which have issued a threshold number of flow control events.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: John S. Howard, John I. Garney
  • Patent number: 6952429
    Abstract: A method of and apparatus for communicating data using a hub. The method includes determining a first estimated unused capacity left in a first frame in which a second transaction is to be performed between a hub and an agent. The method then includes determining an amount of a first data that can fit into the estimated unused capacity and that is to be sent to the hub during a first transaction and then sent by the hub to the agent during the second transaction. The method also includes sending the first data to the hub during the first transaction.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Patent number: 6925015
    Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: John I. Garney, David G. Chow, Rick Coulson
  • Patent number: 6920533
    Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, John I. Garney, Jeanna N. Matthews, Robert J. Royer
  • Patent number: 6889265
    Abstract: An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: John I. Garney, Brian A. Leete
  • Patent number: 6886062
    Abstract: A system and method are disclosed providing for broadened time constraints under USB 2.0 protocol, enabling extended cable spans, in addition to other benefits. The present invention in one embodiment utilizes ‘split transactions’ to take advantage of the relaxed latency requirements of this scheme, in addition to utilizing the 80/20 transaction ratio for USB 2.0 microframes. Another embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to some number, ‘N’, of microframes. A further embodiment takes advantage of the fact that under USB 2.0, no transaction can span from one frame to the next, freeing one extra microframe per frame by virtue of phase shifting a slave device into appropriate synchnronization. Lastly, an embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to a full frame (eight microframes).
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventor: John I. Garney
  • Publication number: 20040225826
    Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.
    Type: Application
    Filed: June 4, 2004
    Publication date: November 11, 2004
    Applicant: Intel Corporation (a Delaware corporation)
    Inventors: Robert J. Royer, John I. Garney
  • Patent number: 6813251
    Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Patent number: 6792495
    Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Patent number: 6782484
    Abstract: A system and method are disclosed for power management that reduces computer power consumption by causing a low power state (‘suspend’ mode) to be entered by specific, peripheral device-related computer components, wherein the components enter the suspend mode after a short period of peripheral device inactivity and are able to resume to an ‘active’ mode quickly without losing information entered into the peripheral device during the transition from the suspend mode to the active mode. To prevent loss of information during the transition, a peripheral memory device is utilized to store the information inputted during the transition and to deliver the information upon reaching the active mode.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Steve B. McGowan, John I. Garney
  • Patent number: 6771664
    Abstract: A method of and apparatus for communicating data using a hub. The method includes determining a first estimated unused capacity left in a first frame in which a second transaction is to be performed between a hub and an agent. The method then includes determining an amount of a first data that can fit into the estimated unused capacity and that is to be sent to the hub during a first transaction and then sent by the hub to the agent during the second transaction. The method also includes sending the first data to the hub during the first transaction.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Publication number: 20040123019
    Abstract: In one embodiment, the present invention includes a method to select a desired configuration parameter for an option read-only memory (ROM) coupled to a system; obtain a code module corresponding to the desired configuration parameter; and provide the code module to the option ROM to dynamically change a portion of code stored in the option ROM. More so, in certain embodiments the present invention permits an option ROM to monitor disk requests in a pre-boot environment.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventor: John I. Garney
  • Publication number: 20040111543
    Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors where split-isochronous transaction descriptors are supported.
    Type: Application
    Filed: December 2, 2003
    Publication date: June 10, 2004
    Inventors: Brian A. Leete, John I. Garney
  • Publication number: 20040100828
    Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 27, 2004
    Inventors: John I. Garney, David G. Chow, Rick Coulson
  • Publication number: 20040088481
    Abstract: A disk cache may include a volatile memory such as a dynamic random access memory and a nonvolatile memory such as a polymer memory. When a cache line needs to be allocated on a write, the polymer memory may be allocated and when a cache line needs to be allocated on a read, the volatile memory may be allocated.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Inventor: John I. Garney
  • Patent number: 6728801
    Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: April 27, 2004
    Assignee: Intel Corporation
    Inventors: Brian A. Leete, John I. Garney
  • Publication number: 20040008684
    Abstract: A method of and apparatus for communicating data using a hub. The method includes determining a first estimated unused capacity left in a first frame in which a second transaction is to be performed between a hub and an agent. The method then includes determining an amount of a first data that can fit into the estimated unused capacity and that is to be sent to the hub during a first transaction and then sent by the hub to the agent during the second transaction. The method also includes sending the first data to the hub during the first transaction.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 15, 2004
    Inventors: John I. Garney, John S. Howard