Abstract: A system and method for serial bus budget development and maintenance. The present invention relates to a method for budgeting transactions under a Universal Serial Bus (USB) protocol, utilizing split transactions, such as USB 2.0. The present invention provides for budgeting transactions occurring across a high-speed to full/low-speed translation, accommodating the full/low speed transactions as well as high-speed splits and data overhead in accordance with USB protocol.

Abstract: A method and apparatus for generating stereoscopic displays in a computer system. Each frame in a sequence of frames includes a left image and a right image, and each image includes a plurality of pixels. Depth information for objects depicted in the display is stored in a z buffer. Either the left image or the right image is computed as an approximation of the other using the depth information stored in the z buffer. The approximated image is alternated between the left and the right image on a frame-by-frame basis, so that the left and right image are each approximated every other frame. Pixels which are not filled in the approximated image are assigned values based on the corresponding pixels in the same (non-approximated) image from the preceding frame.

Abstract: A bus controller and its associated device drivers are provided to a digital system to operate and control a peripheral bus, including the selective operation of at least a first portion of the peripheral bus in a store-and-forward manner. The device drivers include a number of programming instructions. Upon programmed with the programming instructions, a digital system is enabled to operate the bus controller to facilitate communication with a first bus agent in this first portion. The programming instructions package a number of request packets destined for the first bus agent into a multi-packet package, schedule the multi-packet package to be transmitted in bulk, at a first communication speed, to a first hub in the first portion, for the first hub to buffer the request packets, and then forward the request packets to the first bus agent, on a packet-by-packet basis and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed.

Abstract: Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced.

Abstract: An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor, determining a current state for a transaction based on the transaction descriptor, and preventing the transaction from starting if the current state indicates the transaction has not already started.

Abstract: A digital system is provided with a bus controller to operate and control a peripheral bus, wherein the bus controller selectively operates at least a first portion of the peripheral bus in a store-and-forward manner. The bus controller facilitates communication with a first bus agent in this first portion by sending a number of request packets destined for the first bus agent to a first hub in the first portion, in an integrated multi-packet form, in bulk, and at a first communication speed. The first hub buffers the request packets, and then forwards the request packets to the first bus agent, on a packet-by-packet basis, and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed.

Abstract: System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node. When a save place node is encountered in a first frame, the traversing jumps to a destination node pointed to by the save place node in a second frame, and continues the traversing there. When a restore place node is encountered when traversing the nodes in the second frame, the traversing returns to the node after the save place node in the first frame and continues the processing in the first frame. The method may be implemented on a system that comprises a processor, a memory, an internal bus, and an external bus controller. The external bus controller and the external bus data may support one or more versions of the Universal Serial Bus standard.

Abstract: A nonvolatile memory module. The module includes a nonvolatile memory array and a connector allowing the array to make connection with a host system. A memory controller operates to either create an image of a nonvolatile intermediate memory in response to an imaging request or populate a nonvolatile intermediate memory in response to an installation request.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors. Further presented is a method including determining whether a queue head has less than or equal to a predetermined packet size and whether a period is one of greater than and equal to a predetermined schedule window. The method includes storing contents of a current entry in a frame list in a next pointer in the queue head. Also replacing the current entry in the frame list with a pointer to a new queue head. Many queue heads are directly coupled to the frame list.

Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the bus is bounded, and establishing an isochronous interface between at least two devices, the isochronous interface supporting an X-T contract. A number of isochronous transactions and corresponding return transactions delivered across the bus is measured during a specified time interval.

Abstract: A computer system provides for the use of isochronous interrupts by devices coupled with the system. Isochronous interrupt requests are received by an interrupt controller during a first time period, recorded, and executed during a second time period. The devices are equipped to handle the delay in interrupt execution. The interrupt controller is set to service isochronous interrupts on a periodic basis. The interrupt controller may flexibly schedule the execution of the isochronous interrupt request at any time during the second time period.

Abstract: A system and method are disclosed providing for broadened time constraints under USB 2.0 protocol, enabling extended cable spans, in addition to other benefits. The present invention in one embodiment utilizes ‘split transactions’ to take advantage of the relaxed latency requirements of this scheme, in addition to utilizing the 80/20 transaction ratio for USB 2.0 microframes. Another embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to some number, ‘N’, of microframes. A further embodiment takes advantage of the fact that under USB 2.0, no transaction can span from one frame to the next, freeing one extra microframe per frame by virtue of phase shifting a slave device into appropriate synchnronization. Lastly, an embodiment of the present invention improves timing constraints by providing a delay between start splits and complete splits equal to a full frame (eight microframes).

Abstract: A system and method for serial bus budget development and maintenance. The present invention relates to a method for budgeting transactions under a Universal Serial Bus (USB) protocol, utilizing split transactions, such as USB 2.0. The present invention provides for budgeting transactions occurring across a high-speed to full/low-speed translation, accommodating the full/low speed transactions as well as high-speed splits and data overhead in accordance with USB protocol.

Abstract: A method and apparatus for traversing a schedule with a bus master, the schedule having a plurality of elements, each element having information pertaining to one of a plurality of endpoints; executing transactions on a bus in accordance with the information pertaining to the plurality of endpoints; counting flow control events issued by individual endpoints; and skipping elements in the traversal of the schedule, the elements being skipped corresponding to endpoints which have issued a threshold number of flow control events.

Abstract: Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. According to one embodiment of the present invention, the transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link. According to another embodiment of the present invention, a first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent.

Abstract: A system and method are disclosed for power management that reduces computer power consumption by causing a low power state (‘suspend’ mode) to be entered by specific, peripheral device-related computer components, wherein the components enter the suspend mode after a short period of peripheral device inactivity and are able to resume to an ‘active’ mode quickly without losing information entered into the peripheral device during the transition from the suspend mode to the active mode. To prevent loss of information during the transition, a peripheral memory device is utilized to store the information inputted during the transition and to deliver the information upon reaching the active mode.

Abstract: Access to a memory is arbitrated by defining a schedule period having service periods for isochronous and asynchronous memory requests. Received isochronous requests are serviced during their respective service periods, and if an asynchronous request is received during an isochronous service period , the isochronous service period is suspended and the asynchronous request is serviced, provided that time remains in the asynchronous service period or there is no isochronous request pending. Otherwise, service of the asynchronous request is delayed until the next schedule period. Service time for isochronous request are therefore guaranteed and scheduled around asynchronous memory request. If there are any maintenance events signaled, the service period for the asynchronous request may be correspondingly decreased while the maintenance event is performed.