Patents by Inventor John M. Lauffer
John M. Lauffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9451693Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.Type: GrantFiled: August 5, 2011Date of Patent: September 20, 2016Inventors: Rabindra N. Das, Voya R. Markovich, John M. Lauffer, Roy H. Magnuson, Konstantinos I. Papathomas, Benson Chan
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Patent number: 8607445Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.Type: GrantFiled: June 14, 2012Date of Patent: December 17, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin
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Patent number: 8502082Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.Type: GrantFiled: August 31, 2005Date of Patent: August 6, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John M. Lauffer
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Patent number: 8501575Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.Type: GrantFiled: October 22, 2010Date of Patent: August 6, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
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Publication number: 20130033827Abstract: A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Rabindra N. Das, Voya R. Markovich, John M. Lauffer, Roy H. Magnuson, Konstantinos I. Papathomas, Benson Chan
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Patent number: 8299371Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.Type: GrantFiled: December 20, 2010Date of Patent: October 30, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr.
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Publication number: 20120223047Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.Type: ApplicationFiled: October 22, 2010Publication date: September 6, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
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Patent number: 8247703Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.Type: GrantFiled: November 3, 2010Date of Patent: August 21, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich
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Patent number: 8242376Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.Type: GrantFiled: August 11, 2010Date of Patent: August 14, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, Michael Wozniak
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Patent number: 8240027Abstract: A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.Type: GrantFiled: January 16, 2008Date of Patent: August 14, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Frank D. Egitto, John S. Kresge, John M. Lauffer
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Publication number: 20120152605Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich, James J. McNamara, JR.
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Patent number: 8144480Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.Type: GrantFiled: March 10, 2010Date of Patent: March 27, 2012Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
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Publication number: 20110173809Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, JR., Peter A. Moschak
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Patent number: 7977034Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: GrantFiled: January 20, 2010Date of Patent: July 12, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
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Patent number: 7897877Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.Type: GrantFiled: May 23, 2006Date of Patent: March 1, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
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Publication number: 20110043987Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.Type: ApplicationFiled: November 3, 2010Publication date: February 24, 2011Inventors: Rabindra N. Das, John M. Lauffer, Voya R. Markovich
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Publication number: 20110017498Abstract: A photosensitive dielectric composition adapted for forming a dielectric film layer for use in a circuitized substrate is provided according to one embodiment of the invention, the composition including an epoxide bearing component including at least one polyepoxide resin curable by electromagnetic radiation, a cyanate ester, a flexibilizer, a nanostructured toughener, a photoinitiator in a predetermined amount by weight of the resin component, and a ceramic filler, the photosensitive dielectric composition forming the dielectric film layer having no solvent therein. In an alternative embodiment, a heat activated dielectric composition is provided which is curable by heat and includes an epoxide bearing component including at least one polyepoxide resin curable by heat, a cyanate ester, a flexibilizer, a nanostructured toughener, a heat activated curing agent for accelerating reaction of the cyanate ester and polyepoxide resin components, and a ceramic filler.Type: ApplicationFiled: July 27, 2009Publication date: January 27, 2011Inventors: John M. Lauffer, Voya R. Markovich, Kostas I. Papathomas
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Patent number: 7870664Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.Type: GrantFiled: May 2, 2007Date of Patent: January 18, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Vova R. Markovich
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Publication number: 20100328868Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.Type: ApplicationFiled: August 11, 2010Publication date: December 30, 2010Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: John M. Lauffer, Voya R. Markovich, Michael Wozniak
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Patent number: 7841741Abstract: An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp.Type: GrantFiled: April 2, 2007Date of Patent: November 30, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John E. Kozol, John M. Lauffer, How T. Lin